Neoway N720 OpenLinux - Figure 3-26 PCM Connection; Figure 3-27 PCM Sync Signal Timing in Primary Mode; Figure 3-28 PCM Data Input Timing in Primary Mode; Figure 3-29 PCM Data Output Timing in Primary Mode

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
37
Figure 3-26 PCM connection
PCM_DOUT
PCM_DIN
PCM_SYNC
PCM_CLK
N720 module
Codec
PCM_DIN
PCM_DOUT
PCM_SYNC
PCM_CLK
The guidelines of schematic design and PCB layout are the same as those of I2S.
The PCM interface supports only standard modes.
Figure 3-27 PCM sync signal timing in primary mode
PCM_SYNC
t(sync)
t(syncd)
t(synca)
Figure 3-28 PCM data input timing in primary mode
t(sus
ync)
t(hsync)
t(clk)
t(clkh) t(clkl)
PCM_CLK
PCM_SYNC
PCM_DIN
MSB
LSB
t(sudin)
t(hdin)
Figure 3-29 PCM data output timing in primary mode
t(clk)
t(clkh) t(clkl)
PCM_CLK
PCM_SYNC
PCM_DOUT LSB
t(zdout)
t(susync
)
t(hsync)
t(pdout
)
t(pdout
)