Neoway N720 OpenLinux - Figure 3-33 SPI Connection

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
40
SPI_MISO_BLSP2
85
DI
Master input
Leave this pin floating if it is not used.
SPI_MOSI_BLSP2
86
DO
Master output
Leave this pin floating if it is not used.
SPI_CS_N_BLSP2
87
DO
Chip select
Leave this pin floating if it is not used.
The SPI interface operates at 1.8V. It supports a maximum frequency of 50 MHz and only host mode.
Figure 3-33 and table show the SPI connection.
Figure 3-33 SPI connection
SPI_MOSI
SPI_CS_N
SPI_CLK
N720 module
(host)
SPI_MISO
MOSI
MISO
CLK
CS
SPI device
(device)
Schematic Design Recommendations

Note the SPI signal direction.

If the levels of slave SPI device and N720 OpenLinux do not match, add a level shifting circuit.
Refer to Figure 3-20 if the SPI speed does not exceed 20 MHz. Select other high-speed level
shifting chipsets if the speed exceeds 20 MHz.
PCB Design Guidelines

Do not cross other traces if possible. If crossing is inevitable, route the SPI traces perpendicular
to other traces.

Keep SPI traces far away from areas that might introduce ESD.

Surround signal traces with ground.
Figure 3-34 and Table 3-9 shows SPI timing and parameters respectively.