Neoway N720 OpenLinux - Figure 3-39 Connection between MDIO and PHY; Figure 3-40 MDIO Input Timing; Figure 3-41 MDIO Output Timing

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N720 OpenLinux

Hardware User Guide

Figure 3-39 Connection between MDIO and PHY

MDIO_DATA

MDIO_CLK

ETH_RST_N

ETH_INT_N

N720 module

MDIO_DATA

MDIO_CLK

RST_N

INT_N

PHY chipset

UIM2_VCC

1.5kΩ

10kΩ

VDD_1P8

MDIO can control one MAC or up to 32 PHY devices. It supports a maximum frequency of 2.5 MHz

and 1.8V/2.85V auto-adaption. Figure 3-40 and Figure 3-41 show MDIO input/output timing.

Figure 3-40 MDIO input timing

Figure 3-41 MDIO output timing

ViL(MAX)

ViH(MIN)

10ns MIN 10ns MIN

ViL(MAX)

ViH(MIN)

MDIO_CLK

MDIO_DATA

ViL(MAX)

ViH(MIN)

0ns MIN

300ns MAX

ViL(MAX)

ViH(MIN)

MDIO_CLK

MDIO_DATA

Main Page

Table of Contents3
About N720 Openlinux11
Product Overview11
Table 1-1 Variant and Frequency Bands11
Block Diagram12
Basic Features13
Figure 1-1 Block Diagram13
Module Pins16
Pad Layout16
Figure 2-1 N720 Openlinux Pin Definition (Top View)16
Table 2-1 IO Types and Level Features17
Table 2-2 Pin Description18
Application Interfaces25
Power Interface25
Vbat25
Figure 3-1 Current Peaks and Voltage Drops26
Figure 3-2 Recommended Design 126
Figure 3-3 Recommended Design 227
Figure 3-4 Recommended Design 328
Figure 3-5 Recommended Design 428
Vdd_1P829
Control Interfaces30
Pwrkey_N30
Table 3-1 VDD_1P8 Electrical Features30
Figure 3-6 Reference Design of Startup Controlled by Button31
Figure 3-7 Reference Design of Startup Controlled by MCU31
Figure 3-8 Reference Design of Automatic Start Once Powered up31
Figure 3-9 N720 On/Off Timing32
Reset_N33
Figure 3-10 Reset Controlled by Button33
Figure 3-11 Reset Circuit with Triode Separating33
Figure 3-12 Reset Timing of N720 Openlinux33
Peripheral Interfaces34
Usb34
Table 3-2 Compliant Standards of Peripheral Interfaces34
Figure 3-13 USB Connection35
Figure 3-14 Reference Design of USB OTG Function35
Usim36
Figure 3-15 Reference Design of USIM Card Interface36
Uart37
Figure 3-16 Reference Design of UART Connection (with Flow Control)38
Figure 3-17 Reference Design of UART Connection (Without Flow Control)38
Figure 3-18 Recommended Level Shifting Circuit 139
Figure 3-19 Recommended Level Shifting Circuit 240
Sdc41
Figure 3-20 Recommended Level Shifting Circuit 341
Figure 3-21 SD Connection42
Table 3-3 SD Card Feature Parameters42
Figure 3-22 SDC SDR Timing43
Figure 3-23 SDC DDR Timing44
Table 3-4 Timing Parameters of SDC Interface44
I2S/Pcm45
Figure 3-24 I2S Connection45
Figure 3-25 I2S Timing46
Table 3-5 Timing Parameters of I2S Interface46
Table 3-6 PCM Work Modes46
Figure 3-26 PCM Connection47
Figure 3-27 PCM Sync Signal Timing in Primary Mode47
Figure 3-28 PCM Data Input Timing in Primary Mode47
Figure 3-29 PCM Data Output Timing in Primary Mode47
Figure 3-30 PCM Sync Signal Timing in Auxiliary Mode48
Figure 3-31 PCM Data Input Timing in Auxiliary Mode48
Table 3-7 Parameters of PCM Timing in Primary Mode48
Spi49
Figure 3-32 PCM Data Output Timing in Auxiliary Mode49
Table 3-8 Parameters of PCM Timing in Auxiliary Mode49
Figure 3-33 SPI Connection50
I2C51
Figure 3-34 SPI Timing51
Table 3-9 Timing Parameters of SPI Interface51
Table 3-10 I2C Feature Parameters51
Figure 3-35 I2Cconnection52
Figure 3-36 I2C Data Transmission52
Figure 3-37 I2C Timing53
Table 3-11 I2C Timing Parameters (Standard Mode)53
Table 3-12 I2C Timing Parameters (Fast Mode)54
Table 3-13 I2C Timing Parameters (Fast Mode Plus)54
Network and Connection55
Ethernet55
Figure 3-38 SGMII Connection55
Figure 3-39 Connection between MDIO and PHY57
Figure 3-40 MDIO Input Timing57
Figure 3-41 MDIO Output Timing57
Wlan58
Table 3-14 SDIO/WLAN Feature Parameters58
Figure 3-42 WLAN Connection59
Figure 3-43 SDIO SDR Timing60
Figure 3-44 SDIO DDR Timing60
Table 3-15 Timing Parameters of SDIO/WLAN Interface60
Bluetooth61
RF Interface62
Figure 3-45 Bluetooth Connection62
ANT_MAIN/ANT_DIV Antenna Interface63
Figure 3-46 L Network63
Figure 3-47 Split Capacitor Network63
Figure 3-48 Pi Network64
ANT_GNSS Interface65
Figure 3-49 Recommended RF PCB Design 165
Figure 3-50 Recommended RF PCB Design 265
Figure 3-51 GNSS RF Structure65
Figure 3-52 Reference Design of Passive GNSS Antenna66
Figure 3-53 Reference Design of Active GNSS Antenna67
Antenna Assembling68
Figure 3-54 Reference Layout of GNSS Antenna Traces68
Gpio69
Figure 3-55 Specifications of MM9329-2700RA169
Figure 3-56 RF Connections69
MUX Interfaces70
Table 3-16 MUX Pins70
Other Interfaces73
Gnss_Lna_En73
Adc73
Ring73
Figure 3-57 Pulse Wave for an Incoming Call73
Dtr74
Figure 3-58 RING Indicator for SMS74
Figure 3-59 Process of Entering Sleep Mode74
Figure 3-60 Incoming Call Service Process75
Figure 3-61 Outgoing Call Service Process75
Figure 3-62 Process of Exiting from Sleep Mode75
Usb_Boot76
Figure 3-63 Reference Design of USB_BOOT76
Electric Feature and Reliability77
Electric Features77
Temperature Features77
Table 4-1 Electric Features77
Table 4-2 Temperature Features77
ESD Protection78
Table 4-3 ESD Protection Features78
RF Features79
Operating Bands79
Table 5-1 Operating Bands79
TX Power and RX Sensitivity80
Table 5-2 RF TX Power80
Table 5-3 RF RX Sensitivity81
GNSS Feature82
Mechanical Features84
Dimensions84
Figure 6-1 N720 Dimensions84
Label85
Pack85
Figure 6-2 N720 Openlinux Label85
Tray86
Figure 6-3 N720 Openlinux Packing with Vacuum Bag and Tray86
Figure 6-4 Packaging Process86
Moisture87
Mounting N720 Onto the Application Board88
Bottom Dimensions88
Figure 7-1 Bottom View88
Application Foot Print89
Stencil89
Solder Paste89
Figure 7-2 Recommended Application Foot Print (Top View)89
SMT Furnace Temperature Curve90
Figure 7-3 SMT Furnace Temperature Curve90
Safety Recommendations91
A Conformity and Compliance92
Approvals92
Chinese Notice92
CCC Class a Digital Device Notice92
Environmental Protection Notice92
B Abbreviation93

Neoway N720 OpenLinux - Figure 3-39 Connection between MDIO and PHY; Figure 3-40 MDIO Input Timing; Figure 3-41 MDIO Output Timing

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