Neoway N720 OpenLinux - Page 56

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
46
Schematic Design Recommendations

Note the match of SGMII signals.

Connect 0.1 μF DC blocking capacitors to SGMII pins in series.
PCB Design Guidelines

Place these DC blocking capacitors close to the RX pins on the PCB, e.g. C1 and C2 close to
the PHY chipset while C3 and C4 close to the module.

Keep the length difference of TX positive and negative signal lines. The difference should be
within 0.7mm.

Keep the length difference of RX positive and negative signal lines. The difference should be
within 0.7mm.

Control the impedance of the TX and RX traces separately, and the differential impedance
ranges from 80Ω to 120Ω.

Trace spacing between TX and RX should be larger than 3x trace widths. Trace spacing
between SGMII and other traces should be larger than 3x trace widths.
MDIO and PHY
Signal
Pin
I/O
Function
Remarks
USIM2_VCC
21
PO
Power supply for MDIO data
line to be pulled up to
Compatible with 1.8V/3V UIM
card
SGMII_MDIO_CLK
22
DO
MDIO clock
SGMII_MDIO_DATA
23
B
MDIO data IO
Add a 1.5kΩ resistor between
this pin and UIM2_VCC.
ETH_REST_N
24
DO
Ethernet PHY chipset reset
ETH_INT_N
25
DI
Ethernet PHY chipset interrupt
MDIO and PHY chipset signals share the same pins with USIM2. The hardware does not support both
functions simultaneously. Figure 3-39 shows the connection between MDIO and PHY chipset.