Neoway N720 OpenLinux - Page 5

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
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Table of Figures
Figure 1-1 Block Diagram .................................................................................................................. 3
Figure 2-1 N720 OpenLinux pin definition (Top View) ....................................................................... 6
Figure 3-1 Current peaks and voltage drops ................................................................................... 16
Figure 3-2 Recommended design 1 ................................................................................................. 16
Figure 3-3 Recommended design 2 ................................................................................................. 17
Figure 3-4 Recommended design 3 ................................................................................................. 18
Figure 3-5 Recommended design 4 ................................................................................................. 18
Figure 3-6 Reference design of startup controlled by button ........................................................... 21
Figure 3-7 Reference design of startup controlled by MCU ............................................................. 21
Figure 3-8 Reference design of automatic start once powered up .................................................. 21
Figure 3-9 N720 on/off timing ........................................................................................................... 22
Figure 3-10 Reset controlled by button ............................................................................................ 23
Figure 3-11 Reset circuit with triode separating ............................................................................... 23
Figure 3-12 Reset timing of N720 OpenLinux .................................................................................. 23
Figure 3-13 USB connection ............................................................................................................ 25
Figure 3-14 Reference design of USB OTG function ....................................................................... 25
Figure 3-15 Reference design of USIM card interface ..................................................................... 26
Figure 3-16 Reference design of UART connection (with flow control) ........................................... 28
Figure 3-17 Reference design of UART connection (without flow control) ...................................... 28
Figure 3-18 Recommended level shifting circuit 1 ........................................................................... 29
Figure 3-19 Recommended level shifting circuit 2 ........................................................................... 30
Figure 3-20 Recommended level shifting circuit 3 ........................................................................... 31
Figure 3-21 SD connection .............................................................................................................. 32
Figure 3-22 SDC SDR timing ........................................................................................................... 33
Figure 3-23 SDC DDR timing ........................................................................................................... 34
Figure 3-24 I2S connection .............................................................................................................. 35
Figure 3-25 I2S timing ...................................................................................................................... 36