Neoway N720 - Figure 2-25 PCM Data Input Timing; Figure 2-26 PCM Data Output Timing; Table 2-4 Timing Parameters of PCM Interface

N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd 30
Figure 2-25 PCM data input timing
t(sus
ync)
t(hsync)
t(clk)
t(clkh) t(clkl)
PCM_CLK
PCM_SYNC
PCM_DIN
MSB
LSB
t(sudin)
t(hdin)
Figure 2-26 PCM data output timing
t(clk)
t(clkh) t(clkl)
PCM_CLK
PCM_SYNC
PCM_DOUT
MSB
LSB
t(zdout)
t(susync)
t(hsync)
t(pdout)
t(pdout)
Table 2-4 Timing parameters of PCM interface
Timing Parameter
Min.
Typical
Max.
Unit
t(sync)
PCM_SYNC cycle
-
125
-
ns
t(synca)
PCM_SYNC valid time
-
488
-
ns
t(syncd)
PCM_SYNC invalid time
-
124.5
-
ns
t(clk)
PCM_CLK cycle
-
488
-
ns
t(clkh)
PCM_CLK high time
-
244
-
ns
t(clkl)
PCM_CLK low time
-
244
-
ns
t(susync)
Set-up time from PCM_SYNC high
PCM_CLK low
-
122
-
ns
t(sudin)
Set-up time from PCM_DIN high to
PCM_CLK low
60
-
-
ns
t(hdin)
Hold time from PCM_CLK low to
PCM_DIN high
10
-
-
ns
t(pdout)
Delay time from PCM_CLK high to
PCM_DOUT low
-
-
60
ns
t(zdout)
Delay time from PCM_CLK low to
PCM_DOUT high impedance
-
160
-
ns