Neoway N720 - 2.7.2 I2 C; 2.8.1 SDIO

N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd 31
I2S_MCLK is the main clock referred by the audio system clock. When the PCM interface is used as the
master device, PCM_CLK is configured as the output clock signal and I2S_MCLK is configured as the
main clock signal of the system. When the PCM interface is used as the slave device, PCM_CLK is
configured as the input clock signal and it should be synchronous to the I2S_MCLK.
2.7.2 I2C
Signal
Pin No.
I/O
Function
Remarks
I2C_SDA
81
IO
I2C data
Connected to the power supply via a pull-up resistor
internally. Leave them pin unconnected if they are
not used.
I2C_SCL
82
DO
I2C clock
The I2C interface complies with I2C Specification, version5.0, October 2012. It supports master mode
only and supports a rate of up to 3.4 Mbps. Its reference high level is 1.8V.
2.8 WLAN Interfaces
2.8.1 SDIO
Signal
Pin No.
I/O
Function
Remarks
SDIO_CMD
54
IO
Control signal of
SDIO interface
Leave this pin unconnected if it is not used.
SDIO_CLK
55
DO
Clock signal of
SDIO interface
Leave this pin unconnected if it is not used.
SDIO_DATA0
56
IO
SDIO data bit 0
Leave this pin unconnected if it is not used.
SDIO_DATA1
57
IO
SDIO data bit 1
Leave this pin unconnected if it is not used.
SDIO_DATA2
58
IO
SDIO data bit 2
Leave this pin unconnected if it is not used.
SDIO_DATA3
59
IO
SDIO data bit 3
Leave this pin unconnected if it is not used.
The SDIO interface of the N720 module supports the SDIO 3.0 interface protocol and supports 1.8V. The
following figure shows the SDIO connection.