Nvidia JETSON TX2 User Manual

NVIDIA Jetson TX2/TX2i OEM Product Design Guide
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618 40
Figure 23: Display Backlight/Control Connections
Jetson TX2/TX2i
Tegra
LCD_BKLT_EN
LCD0_BKLT_PWM
LCD1_BKLT_PWM
LCD_TE
LCD_VDD_EN
eDP
GPIO_EDP0
SYS
GPIO_DIS3
GPIO_DIS0
GPIO_DIS5
GPIO_DIS1
Backlight
Control
B2 6
A25
B2 8
B2 7
A24
Tearing Effect
Display
Power Enable
MIPI DSI / CSI Design Guidelines
Table 35. MIPI DSI & CSI Interface Signal Routing Requirements
Parameter
Requirement
Units
Notes
Max Frequency/Data Rate (per data lane) HS (DSI)
HS (CSI)
LP
0.75 / 1.5
1.25 / 2.5
10
GHz/Gbps
MHz
Number of Loads
1
load
Max Loading (per pin)
10
pF
Reference plane
GND
See Note 1
Breakout Region Impedance (Single Ended)
45-50

±15%
Max PCB breakout delay
48
ps
Trace Impedance Diff pair / Single Ended
90-100 / 45-50

Via proximity (Signal to reference)
< 3.8 (24)
mm (ps)
See Note 2
Trace spacing Microstrip / Stripline
2x / 2x
dielectric
Max Trace Delay 1 Gbps
1.5 Gbps
2.5 Gbps
1100
800
350
mm (ps)
See Note 3
Max Intra-pair Skew
1
ps
See Note 3
Max Trace Delay Skew between DQ & CLK
5
ps
See Note 3
Keep critical DSI/CSI related traces including DSI/CSI clock/data traces & RDN/RUP traces away from other signal traces or unrelated power
traces/areas or power supply components
Note:
1. If PWR, 0.01uF decoupling cap required for return current
2. Up to 4 signal Vias can share a single GND return Via
3. If routing to device includes a flex or 2nd PCB, the max trace & skew calculations must include all the PCBs/flex routing
MIPI DSI / CSI Connection Guidelines
Table 36. MIPI DSI Signal Connections
Module Pin Name
Type
Termination
Description
DSI[3:0]_CK+/–
DIFF OUT
DSI Differential Clocks: Connect to CLKn & CLKp pins of receiver. See
connection diagrams for Dual & Split Link Mode configurations.
DSI[3:0]_D[1:0]+/–
DIFF OUT
DSI Differential Data Lanes: Connect to Dn & Dp pins of DSI display. See
connection diagrams for Dual & Split Link Mode configurations.
LCD_TE
I
LCD Tearing Effect: Connect to LCD Tearing Effect pin if supported
LCD_BL_EN
O
LCD Backlight Enable: Connect to LCD backlight solution enable if supported
LCD[1:0]_BKLT_PWM
O
LCD Backlight Pulse Width Modulation: Connect to LCD backlight solution PWM
input if supported
LCD_VDD_EN
O
LCD Power Enable: Connect as necessary to enable appropriate Display power
supply(ies).
Table 37. Recommended DSI observation (test) points for initial boards
Test Points Recommended
Location
One for each signal line.
Near display. Panel connector pins can be used if accessible.
Note:
Test points must be done carefully to minimize signal integrity impact. Avoid stubs & keep pads small & near signal traces

Nvidia JETSON TX2 Specifications

General

Brand	Nvidia
Model	JETSON TX2
Category	Microcontrollers
Language	English