NXP Semiconductors MPC5777M Safety Manual

Safety Manual for MPC5777M, Rev. 1.1
NXP Semiconductors2
Table of Contents
1 Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.1 Mission profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.2 Functional safety – ISO 26262 compliance. . . . . . . . . . .4
2.3 Safety goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.3.1 Safe state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.4 Correct operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.5 Failure indication signaling . . . . . . . . . . . . . . . . . . . . . . .6
2.6 Failure indication time . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.6.1 Minimum failure indication time . . . . . . . . . . . . . .7
2.7 Failure handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3 Functional safety requirements for application software. . . . . .9
3.1 Disabled modes of operation . . . . . . . . . . . . . . . . . . . . .9
3.1.1 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.1.2 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.2 Initial checks and configurations . . . . . . . . . . . . . . . . . .10
3.2.1 I/O ball configuration . . . . . . . . . . . . . . . . . . . . .10
3.2.2 MCU configuration. . . . . . . . . . . . . . . . . . . . . . .11
3.2.3 Mode Entry (MC_ME) . . . . . . . . . . . . . . . . . . . .12
3.2.4 Start-up configuration check . . . . . . . . . . . . . . .13
3.2.5 Dual core lockstep mode . . . . . . . . . . . . . . . . . .13
3.2.6 FCCU fault reaction configuration . . . . . . . . . . .13
3.2.7 Reset Generation Module (MC_RGM) . . . . . . .15
3.2.8 Self-test completion . . . . . . . . . . . . . . . . . . . . . .17
3.2.9 MEMU initial checks . . . . . . . . . . . . . . . . . . . . .20
3.2.10 Flash memory configuration and tests. . . . . . . .20
3.2.11 Voltage monitor configuration . . . . . . . . . . . . . .21
3.2.12 Temperature monitoring configuration . . . . . . . .23
3.2.13 Clock monitoring configuration . . . . . . . . . . . . .24
3.2.14 System clock availability . . . . . . . . . . . . . . . . . .25
3.2.15 Clock Generation Module (MC_CGM). . . . . . . .25
3.2.16 PLL generated clocking . . . . . . . . . . . . . . . . . . .26
3.2.17 XBAR configuration . . . . . . . . . . . . . . . . . . . . . .26
3.2.18 Platform flash memory controller. . . . . . . . . . . .26
3.2.19 Wake-Up Unit (WKPU) / External NMI . . . . . . .27
3.2.20 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
3.2.21 Software Watchdog Timer (SWT) . . . . . . . . . . .27
3.2.22 Analog to Digital Converters . . . . . . . . . . . . . . .28
3.2.23 Temperature sensor (TSENS) . . . . . . . . . . . . . .30
3.3 Runtime checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.3.1 General requirements . . . . . . . . . . . . . . . . . . . .30
3.3.2 CRC of configuration registers. . . . . . . . . . . . . .31
3.3.3 XBAR usage . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.3.4 System Memory Protection Unit (SMPU) . . . . .32
3.3.5 Platform flash memory controller. . . . . . . . . . . .33
3.3.6 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.3.7 PRAMC configuration . . . . . . . . . . . . . . . . . . . .35
3.3.8 RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.3.9 ECC Bypass using core registers and Indirect
Memory Access (IMA)38
3.3.10 Decorated Storage Memory Controller (DSMC) 39
3.3.11 Interrupt management . . . . . . . . . . . . . . . . . . . 39
3.3.12 eDMA usage . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.3.13 Reset Generation Module (MC_RGM). . . . . . . 40
3.3.14 Detection of unwanted resets. . . . . . . . . . . . . . 41
3.3.15 Periodic Interrupt Timer (PIT). . . . . . . . . . . . . . 47
3.3.16 System Timer Module (STM) usage . . . . . . . . 47
3.3.17 I/O and Peripheral Bridge. . . . . . . . . . . . . . . . . 47
3.3.18 System Integration Unit Lite (SIUL2) . . . . . . . . 50
3.3.19 GTM Wrapper. . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.20 External Bus Interface (EBI). . . . . . . . . . . . . . . 50
3.3.21 Reading analog inputs . . . . . . . . . . . . . . . . . . . 51
3.3.22 Software Watchdog Timer (SWT) usage . . . . . 51
3.3.23 Communication peripherals . . . . . . . . . . . . . . . 51
3.3.24 Temperature sensor (TSENS) . . . . . . . . . . . . . 52
3.3.25 Analog to Digital Converters . . . . . . . . . . . . . . 52
3.3.26 Mode Entry (MC_ME) . . . . . . . . . . . . . . . . . . . 55
3.3.27 Semaphores (SEMA42) . . . . . . . . . . . . . . . . . . 55
3.4 Operational interference protection . . . . . . . . . . . . . . . 55
3.4.1 Core Memory Protection Unit (CMPU). . . . . . . 55
3.4.2 System Memory Protection Unit (SMPU). . . . . 56
3.4.3 AIPS protection mechanism. . . . . . . . . . . . . . . 56
3.4.4 Register protection (REG_PROT) . . . . . . . . . . 57
3.4.5 Performance (Core_1) and Peripheral (Core_2)
Cores57
4 Functions of external devices for ASIL D applications . . . . . 58
4.1 External reset output . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.2 High impedance outputs . . . . . . . . . . . . . . . . . . . . . . . 58
4.3 External Watchdog (EXWD) . . . . . . . . . . . . . . . . . . . . 59
4.4 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.5 Error Out Monitor (ERRM). . . . . . . . . . . . . . . . . . . . . . 60
4.5.1 Both FCCU pins connected to external device. 61
4.5.2 Single FCCU pin connected to external device 61
5 Address decoding coverage . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2 Test implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3 Obtaining the list of locations to be read . . . . . . . . . . . 69
Memories including block address decoding75
5.4 Test result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Multiple single bit error in the same word-line79
6 Testing All-X in RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.1 Candidate address for testing All-X issue . . . . . . . . . . 81
6.2 ECC checkbit/syndrome coding scheme. . . . . . . . . . . 86
7 Further information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.1 Conventions and terminology . . . . . . . . . . . . . . . . . . . 91
7.2 Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . 91
8 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

NXP Semiconductors MPC5777M Specifications

General

Brand	NXP Semiconductors
Model	MPC5777M
Category	Microcontrollers
Language	English