NXP Semiconductors MPC5777M Safety Manual

Address decoding coverage
Safety Manual for MPC5777M, Rev. 1.1
NXP Semiconductors 69
5.3 Obtaining the list of locations to be read
This section describes, with an example, the different steps to get the list of location to be read. The
procedure starts when a single bit error correction at certain address, i.e. victim address, is reported.
Let assume the victim address is the address 011101100001 in the SRAM.
The first step is to split the victim address in “bit grouping” depending on the decoding structure of the
memory (see Table 4).
Figure 3 shows the bit grouping for the victim address of the example.
Figure 3. Bit grouping of victim address considering the SRAM
With reference to the Table 6, the first locations to be read are the victim address (in red), its
complementary (in yellow) and all locations belonging to the word-line of the victim and complementary
addresses (in grey).
In the next step starting from the victim address, the value of DecD, DecC and DecB is kept unchanged
and all combinations of DecA are considered.
As result three additional word-lines are added to the list (in gray in Table 7).
100 10 11 00 DecD combination
101 10 11 00
DecD combination
110 10 11 00
DecD combination
111 10 11 00
DecD combination
DecD DecC DecB DecA DecE
Victim address
Ah
011 10 11 00 001
row selection column selection
Table 6. Victim address and complement
DecE
DecD DecC DecB DecA 000 001 010 011 100 101 110 111 Description
011 10 11 00
Ah : victim address (red cell)
100 01 00 11
Complementary address
Table 5. Example of back-to-back read to implement test (continued)
DecE
DecD DecC DecB DecA 000 001 010 011 100 101 110 111 Description

NXP Semiconductors MPC5777M Specifications

General

Brand	NXP Semiconductors
Model	MPC5777M
Category	Microcontrollers
Language	English