Safety Manual for MPC5777M, Rev. 1.1
Testing All-X in RAM
NXP Semiconductors86
Example:
1. Find the first address of each type for system RAM:
— ./find_allx_addr 40000000h
RAM base address = 40000000h
All 0s - Addresses with two bits set in the address ECC contribution:
• addr = 40000010h, addr_ecc = 06h
All 1s - Addresses with two bits cleared in the address ECC contribution:
1. addr = 40000008h, addr_ecc = DBh
2. Find the first 5 addresses of each type for system RAM:
— ./find_allx_addr 40000000 5
RAM base address = 40000000h
All 0s - Addresses with two bits set in the address ECC contribution:
1. addr = 40000010h, addr_ecc = 06h
2. addr = 40000038h, addr_ecc = 14h
3. addr = 40000058h, addr_ecc = C0h
4. addr = 40000080h, addr_ecc = 28h
5. addr = 400000F8h, addr_ecc = 21h
All 1s - Addresses with two bits cleared in the address ECC contribution:
1. addr = 40000008h, addr_ecc = DBh
2. addr = 40000098h, addr_ecc = F5h
3. addr = 400000B0h, addr_ecc = E7h
4. addr = 400000C8h, addr_ecc = EEh
5. addr = 400000E0h, addr_ecc = FCh
6.2 ECC checkbit/syndrome coding scheme
The E2E ECC scheme implements a single-error correction, double-error detection (SECDED) code using
the so-called Hsiao odd-weight column criteria. These codes are named for M.Y. Hsiao, an IBM researcher
who published extensively in the early 1970s on SECDED codes better suited for implementation in
protecting (mainframe) computer memories than traditional Hamming codes.
The Hsiao codes are Hamming distance 4 implementations which provide the SECDED capabilities. The
minimum odd-weight constraints defined by Hsiao are relatively simple in the resulting implementation
of the parity check H matrix which defines the association between the data (and address) bits and the
checkbits. They are:
1. There are no all zeroes columns.
2. Every column is distinct.
3. Every column contains an odd number of ones, and hence is “odd weight”.
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