Address decoding coverage
Safety Manual for MPC5777M, Rev. 1.1
NXP Semiconductors 63
5 Address decoding coverage
5.1 Overview
The MPC5777M embeds a hardware mechanism called Single Bit Error Correction and Dual Bit Error
Detection to detect and, if possible, correct failures impacting the RAM array. This hardware measure is
based on a modified Hamming code algorithm.
Faults impacting the addressing logic (for example, addressing faults) generally cause Multi Bit Errors
(MBEs). The MPC5777M does not embed a specific hardware mechanism to manage this type of fault,
but these MBEs can be interpreted by the modified Hamming code algorithm as Single Bit Errors (SBEs).
This may cause a violation of the safety goal.
This chapter explains how, in case of an ECC hit, a software test can differentiate between an SBE and an
MBE due to a permanent fault in the addressing logic.
5.2 Test implementation
The basic mechanism behind addressing fault detection is the ECC with address contribution embedded
in the MPC5777M devices.
Reading from locations affected by permanent addressing faults returns a random pattern. The Diagnostic
Coverage (DC) of the ECC against addressing faults on a single access is about 70%.
To improve this DC, the idea is to perform multiple memory reads in order to trigger the failure mechanism
multiple times, say K, and in multiple locations in such a way that the overall DC increases up to
DC = 1 - (1 - 70% )
K
.
This formula is valid under the assumption the K failures are somehow independent. It is necessary to:
• understand how to trigger K independent failures in case of addressing fault, and
• minimize the number of memory operations, say M, necessary to trigger the K failures.
The described algorithm is focused on the detection of failures affecting RAM address decoder
considering both rows and columns of the array.
To achieve these objectives, user shall know the “hit address” and details on how the memory is
implemented.
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