NXP Semiconductors MPC5777M Safety Manual

Address decoding coverage
Safety Manual for MPC5777M, Rev. 1.1
NXP Semiconductors 75
5.3.1 Memories including block address decoding
Some memories (for example, D-Mem) include a block address decoder. In this case a further step shall
be added to the procedure described in Section 5.3, Obtaining the list of locations to be read.
Figure 4. Bit grouping of victim address considering D-Mem
To describe the needed additional steps, an example is considered. Let’s assume a single bit error is
reported at the hit address 1.110.010.001.001b of the D-Mem.
Following the steps described in Section 5.3, Obtaining the list of locations to be read, the list of locations
to be read in the block containing the hit-address are shown in Table 13 (in gray).
Table 14. First four cells read
DecE
DecD DecC DecB DecA 000 001 010 011 100 101 110 111 Description
000 10 11 00
DecD combination
001 10 11 00
DecD combination
010 10 11 00
DecD combination
011 10 01 00
DecB combination
011 10 11 00
DecB combination
011 00 11 00
DecC combination
011 01 11 00
DecC combination
011 10 11 00
6 4 10 14 16 12 2 8 Ah : victim address (red cell)
011 11 11 00
DecC combination
011 10 11 01
DecA combination
011 10 11 10
DecA combination
011 10 11 11
DecA combination
100 01 00 11
5 3 9 13 15 11 1 7 Complementary address
100 10 11 00
DecD combination
101 10 11 00
DecD combination
110 10 11 00
DecD combination
111 10 11 00
DecD combination
DecC DecB DecA DecE Block
Victim address
Ah
1 110 010 101 001
row selection column selection block selection

NXP Semiconductors MPC5777M Specifications

General

Brand	NXP Semiconductors
Model	MPC5777M
Category	Microcontrollers
Language	English