Functional safety requirements for application software
Safety Manual for MPC5777M, Rev. 1.1
NXP Semiconductors 35
3.3.6.3 Flash memory multibit error
Nonvolatile flash memory is protected with a single-bit correction/double-bit error detection (SEC/DED)
ECC scheme.
Multibit errors can be caused by failures affecting common pieces of the flash memory (for example,
sensing amplifier, read logic). These type of failures lead to random data reads (for example, white noise
on read word). Reading random data is detected as single-bit correction (SBC) and corrected by the ECC
logic
1
. A software mechanism is needed to distinguish between a real SBC and a MBE.
This test consists of executing multiple reads to be run if an SBC event occurs (for example, 4 reads is
sufficient). If the multiple reads trigger additional correctable/noncorrectable errors, the flash memory
contains permanent multibit errors.
Assumption: [SM_FMEDA_073]If an ECC correction occurs, the application shall force the read of a
number of patterns sufficient to trigger other ECC error corrections/detections revealing the actual nature
of the fault (in fact, permanent flash memory control failures typically affects multiple read operations).
[end]
NOTE
The piece of the flash memory which can cause multibit errors are shared by
the Read-While-Write (RWW) partitions of each flash memory. The
multiple read shall be executed out of the affected RWW flash partition (list
of flash memory RWW partitions are shown in the “Memory Map”
chapter’s “Flash memory and overlay RAM map” table of the MPC5777M
Reference Manual’s).
[SCG18.134] Reading 4 patterns is sufficient to reach a DC of about 99% of
coverage. [end]
3.3.6.4 EEPROM emulation
The MPC5777M provides eight blocks (8 × 64 KB) of the flash memory for EEPROM emulation. ECC
events detected on accesses to the EEPROM flash memory blocks are not reported to the MEMU.
Single-bit corrections (SBCs) are performed, but not signaled to the MEMU. MBEs are replaced by a fixed
word (for example, an illegal instruction) and are also not forwarded to the MEMU.
Assumption: [SCG18.063]Software using EEPROM for storage of information will use its own
information redundancy (for example, CRCs) to detect incorrect data returned from the EEPROM
emulation. [end]
3.3.7 PRAMC configuration
PRAMC provides a certain level of configurability on accessing the RAM. Faults in the PRAMC
configuration registers may change PRAMC port priority and, most important, read wait states. Changes
in port priorities, or more wait states, can have an impact on the overall performance, which is typically
1.With a DC of about 70%.
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