Safety Manual for MPC5777M, Rev. 1.1
Functional safety requirements for application software
NXP Semiconductors20
3.2.9 MEMU initial checks
MBISTs report detected faults to the same MEMU reporting block used for System RAM ECC failures.
Errors are in general distinguished between single-bit and multi-bit. However, it is not guaranteed that
single-bit errors found in different steps on the same address are reported as multi-bit errors
Recommendation: The application software can write known error addresses into the MEMU reporting
table to prevent reporting of those errors to the FCCU in case the addresses are accessed again.
3.2.10 Flash memory configuration and tests
MPC5777M provides 8.7 MB of programmable non-volatile (NVM) flash memory with ECC which can
be used for instruction and/or data storage.
Assumption: [SM_FMEDA_036]To detect failures where a wrong or multiple selection targets a different
block while programming, application SW shall configure flash memory blocks as read only when not the
target of a write operation. [end]
NOTE
See the “Program software locking” section in the “Embedded Flash
Memory” chapter of the MPC5777M Reference Manual for details.
The flash memory array integrity self check detects possible latent faults affecting the flash memory array,
including potential data integrity issues, or the logic involved in read operations (for example, sense
amplifiers, column mux’s, address decoder, voltage/timing references). It calculates a MISR signature
over the array content and thus validates the content of the array as well as the decoder logic. The
calculated MISR value is dependent on the array content and must be validated by software.
The array integrity MISR value is calculated after ECC detection and correction. Flash memory ECC logic
accounts for single-bit correction (SBC) opportunities, and will output corrected data into the MISR
calculation.
Single bit correction reporting still occurs in the FLASH_MCR[SBC] bit and the FLASH_ADR during AI
if FLASH_UT0[SBCE] = 1.
The AI breakpoint feature allows to break the Array Integrity Check execution if an event is a single bit
correction or a double bit detection. Array Integrity Check can be resumed by the application after
verifying the source of the correction/error and clearing the respective status bit (for example, MCR[SBC]
or MCR[EER]).
Assumption: [SCG18.032]The application software shall run the flash memory AI at start-up to detect
possible latent faults. [end]
NOTE
See the “Array Integrity Self Check” section in the MPC5777M Reference
Manual for details.
In the event of a user detected single-bit correction through user reads or an array integrity check, a margin
read may be done to check for a possible second bit failing within the selected margin levels.
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