Testing All-X in RAM
Safety Manual for MPC5777M, Rev. 1.1
NXP Semiconductors 87
In defining the H-matrix for this family of devices, these requirements from Hsiao were applied.
Additionally, there are a variety of ECC codeword requirements associated with specific functional
requirements associated with the flash memory that further dictated the specific column definitions. In any
case, the resulting ECC is organized based on 64 data bits plus 29 address bits (the upper bits of the 32-bit
address field minus the 3 bits which select the byte within 64-bit (8-byte) data field.
The basic H-matrix for this (101, 93) code (93 is the total number of “data” bits, 101 is the total number
of data bits (93) plus 8 checkbits) is shown in Table 20. A ‘*’ in Table 20 indicates the corresponding data
or address bit is XOR’d to form the final checkbit value on the left. For 64-bit data writes, the table sections
corresponding to D[63:32], D[31:0], and A[31:3] are logically summed (output of each table section is
XOR’ed) together to the final value driven on the hwchkbit[7:0] outputs. Note that this table uses the AHB
bit numbering convention where bit[0] is the least significant bit.
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