SYSTEM
STRUCTURE
MAIN
MEMO'RY
NON-ADDRESSABLE
MAIN
MEMORY
SCRATCH-PAD
MEMORY
• The
main
memory
of
the
RCA
70/46
Processor
is
the
central
storage
for
both
data
to be processed and
the
controlling instructions. Main
memory
consists
of
planes
of
magnetic cores,
with
each core
representing
one
binary
digit. The smallest addressable
unit
of
information
in
main
memory
is one
byte
(eight
bits).
The first 128 locations
of
main
memory
are
reserved
for
processor use
and
must
not
be used by
the
program.
The
basic cycle time
of
the
70/46
Processor is
the
time
required
to
access
and
transfer
a
halfword
from
main
memory
to
the
memory
register
and
regenerate
the
information
in
main
memory.
The
memory
cycle
time
is 1.44 microseconds,
and
memory is available
in
a 262 KB module.
• A non-addressable
main
memory, is
in
addition to
main
memory
and
cannot
be addressed by
programming.
It
contains
the
subchannel
registers
that
control
the
operation
of
input/output
devices on
the
mUltiplexor
channel. A
set
of
three
32-bit
registers
services each device
on
the
multi-
plexor channel; 256 sub channel
register
sets
and
devices
can
be connected
to
the
multiplexor channel.
•
The
scratch-pad memory is a micromagnetic
storage
device consisting
of
128 four-byte words,
the
cycle time
of
which
is
300 nanoseconds.
Each
word
is scratch-pad memory is uniquely addressed.
The following
registers
are
contained
in
scratch-pad
memory. (See
also Appendix
1.) :
1. Processor Utility Registers - All locations designated
as
processor
utility
registers
are
used by
the
processor
for
program
control
and
cannot
be
used by
the
program.
2.
General Registers - These locations
are
the
general
registers
for
each processor state. These
registers
are
used
by
the
program
for
base addressing,
for
indexing,
or
for
storing
operands.
Note:
The
70/46
Processor
has
four
processor
states
that
pertain
to
system
and
program
interrupts.
3.
Interrupt Mask Registers -
An
Interrupt
Mask
register
for
each
processor
state
permits
or
inhibits
32
interrupt
conditions.
4.
Interrupt Status Registers -
An
Interrupt
Status
register
for
each processor
state
stores
interrupt
identification
information
and
operational control
information.
This
register
contains
indications
of
the
last
state
interrupted,
the
protection key,
the
decimal mode
(USASCII
or
EBCDIC),
the
privileged mode hit,
and
the
supervisor
call identification.
4
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