Block
19
Block 20
Block 21
Block 22
Halt
Device Instruction
Input/Output
Operation
•
If
a
burst
mode operation has been specified,
the
Channel
Address
Word
and
Channel Block Address
(if
T = 1)
are
fetched
from
main
memory
locations 72
through
79
and
stored in
the
channel
address
register
for
the
mUltiplexor channel. Using
the
main
memory
address
specified
in
the
CAW,
the Channel Command Word is fetched
and
stored in
the
channel command
registers
for
the
multiplexor channel.
•
If
a
burst
mode operation
has
not
been specified,
the
Channel Address
Word
and
the
Channel Command Word
are
fetched
from
main
memory
and
stored
in
the
subchannel
registers
in non-addressable
main
memory
for
the
device specified.
•
If
the
condition code is
not
set
to 0, a
test
is
made
to see
if
the
condition
code is
set
to 1.
•
If
the
condition code is
set
to 1,
the
standard
device byte is
transferred
to
the
channel
registers
for
the
channel specified,
the
Start
Device
instruc-
tion is
terminated
and
program
control is
transferred
to
the
next
instruc-
tion. The
input/output
operation is
not
initiated.
Notes on
Start
Device Instruction
1. The channel
status
byte
and
the
standard
device
byte
are
not
stored
if
the
condition codes
are
0,
2, 3.
2.
If
the
specified channel
and
device can be
initiated
(CC = 0)
the
contents of
the
Channel Address Word, Channel Block
Address
(if
T =
1),
and
Channel Command Word
are
loaded into
the
appropriate
channel
registers
and
the
command is
sent
to
the
device.
The
legality
of
the
command is not determined
at
initiation
time.
If
the
device
gets
an
illegal command,
the
operation
is
terminated
and
a channel
interrupt
occurs. The
standard
device byte
(stored
in
the
appropriate
channel
registers
when
the
interrupt
is
taken)
indicates a secondary
indicator. A
Sense command
must
be issued to
bring
the
Sense byte
(s)
into
main
memory. The Sense
byte(s)
indicate
the
illegal operation.
3.
If
execution
of
this
instruction
causes
the
channel
status
byte
or
the
standard
device byte to be stored,
the
program
must
inhibit
inter-
rupts
on
this
channel until
the
status
byte
has
been analyzed
or
moved
from
the
channel registers.
If
interrupts
are
permitted
and
one occurs
the
standard
device byte
and
the
channel
status
byte
are
destroyed.
•
The
Halt
Device
instruction
is a privileged
operation
and
can be exe-
cuted only
if
the
mode
bit
(bit
position 15
of
the
Interrupt
Status
register)
for
the
current
state
is
set
to
O.
This
instruction
is executed
in
the
normal
mode. Continuation
of
program
execution is delayed
until
termination
is
accepted by
the
device control electronics. When
the
device control elec-
tronics
receives
the
termination,
it
causes a channel
interrupt
to occur.
Both
the
channel
number
and
the
device
number
must
be specified
in
the
instruction. Because
the
Channel Address Word is
not
referred
to by
the
Halt
Device instruction,
the
Channel Address Word, Channel Block
Address,
and
a Channel Command Word
are
not
required.
Upon execution
of
a
Halt
Device instruction,
the
following events
occur
(see figure
6).
52
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