RCA 70/46 - Load Positive (LPER) (LPDR)

Load Positive
(LPER) (LPDR)
General Description
Format
(RR Short)
(RR Long)
Condition Code
Interrupt
Action
Notes
Floating-P oint Instructions
• The operand in the floating-point register specified by the second
address
(R
2
)
is loaded into the floating-point register specified by the first
address (R
1
)
and the operand sign is made plus.
0
0
•
•
•
(LPER) 30
Rl
R2
7 8
11 12 15
(LPDR) 20
Rl R2
7 8 11
12 15
o - result mantissa is zero.
I-not used.
2 - result mantissa is
greater than zero.
3-not used.
Address
error:
Specification.
1. The exponent
and mantissa
are unaltered.
2. Short operands do not alter the low -order half of the register specified
by the first address.
208