RCA 70/46 - Load Address (LA)

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Load Address

(LA)

General Description

Format

(RX)

Condition Code

Interrupt Action

Notes

Logical

1 nstructions

• The final main memory address specified

by

the

second operand

(XdBdD

2

)

is loaded into

the

rightmost

24 bits

of

the

general

register

specified by

the

first address

(R

1

).

The leftmost

eight

bits

of

the

register

are

set

to zeros.

The

contents

of

the

registers

specified by

the

X

2

and

B2

fields

are

added

to

the

contents

of

the

D2

field

of

the

instruction to obtain

an

address. This

is

the

address

that

is loaded into

the

register

specified

by

the

first address.

Any

carry

beyond

the

rightmost

24

bits

is ignored.

41

o 7 8

11

12

15

16 19

20

31

• Unchanged.

•

None.

•

1.

All specified address

arithmetic

is computed before loading.

2.

Rh

X

2

and

B2

may

specify

the

same

register;

however Rl only

may

specify

register

o.

3.

This

instruction can be used to

increment

the

low-order 24

bits

of

a

general

register

(other

than

0)

by

the

contents

of

the

D2

field.

The

register

to be incremented is specified

by

R

1

,

and

either

X

2

(with

B2

set

to zero)

or

B2

(with

X!!

set

to zero). Since Rl

and

X

2

or

B2

must

specify

the

same register,

register

zero

cannot

be

incremented

(a

zero in

the

B2

or

X

2

field indicates

that

the

corre-

sponding address component is

absent).

4. Main memory is

not

accessed

by

this

instruction.

181

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