RCA 70/46 - Privileged Operation

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Priority No.

22

23

24

Condition

Privileged

Operation

Operation

Code

Trap

Address

Error

(Cont'd)

Table

9.

Interrupt Conditions (Cont'd)

Flag Bit

221

222

2

23

Explanation

This

interrupt

occurs

when

a

privileged

instruction

is

attempted

and

the

current

processor

state

is

in

non-privileged

mode.

(Bit

position

15

of

the

Interrupt

Status

register

is

set.)

The

instruction

is

suppressed.

The

privileged

instructions

in

the

70/46

Processor

are:

Diagnose

Start

Device

Test

Device

Halt

Device

Check

Channel

Program

Control

Load

Scratch

Pad

Store

Scratch

Pad

Idle

Set

Storage

Key

Insert

Storage

Key

Write

Direct

Read

Direct

~

If

the

Memory

Protect

option

is

installed.

~

If

the

Direct

Control

option

is

installed.

This

interrupt

occurs

when

an

operation

code

that

is

either

not

assigned

or

not

avail-

able

on

the

partiCUlar

processor

is

attempted.

No

operation

is

performed.

The

instruc-

tion

length

code field

of

the

P

counter

of

the

terminated

state

tells

how

far

to

rollback

the

P-count

to

reach

its

value

prior

to

interrupt

as

follows:

ILC

01

10

11

Length in Bytes

Two-bytes

back

Four-bytes

back

Six-bytes

back

Note:

The

ILC

is

always

generated

from

the

operation

code

of

the

instruction.

Three

conditions

cause

an

address

error

interrupt

to

occur.

They

are:

address

error,

specification

error,

and

protection

error.

Addressing

-

An

address

error

(addressing)

interrupt

occurs

when:

1.

An

address

specifies

any

part

of

data,

an

instruction

or

control

word

outside

the

available

main

memory

for

the

particular

installation.

The

instruction

operation

is

terminated

for

an

invalid

data

address,

and

the

results

of

the

instruction

are

unpredictable.

The

instruction

operation

is

suppressed

for

an

invalid

instruction

address.

2.

An

Execute

instruction

specifies

another

Execute

instruction

to

be

performed.

The

operation

is

suppressed.

3.

The

first

operand

address

field

of

an

instruction

designates

an

odd

register

address

for

a

pair

of

general

registers

that

contain

a double

word

operand.

The

operation

is

suppressed.

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