RCA 70/46 - Shift Right Double Logical (SRDL)

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Shift Right Double

Logical

(SRDL)

General Description

Format

(RS)

Condition Code

Interruption

Logical

Instructions

• The

entire

contents

of

the

double-length

operand

(two

general

registers)

- even/odd specified

by

the

first address

(R

1

)

are

shifted

right

the

number

of

bit

positions specified

by

the

second

address

(B

2

/D

2

).

The

R3

field

is ignored.

The second address does

not

refer

to a

main

memory location. The low-

order

six bits

of

the

second address

are

used

as

the

count to specify

the

number

of

bits

of

shifting

to be done. The

remaining

bits

are

ignored.

8e

I

Rl

I

R3

I

B2

I

D2

0

7

8

11

12

15

16

19

20

31

•

Unchanged.

•

Address

error:

Specification.

Notes • 1. The first address

must

specify

an

even-numbered

register.

2. All 64 bits

of

the

double-length

operand

are

shifted.

3. Low-order

bits

are

shifted

out

and

lost.

4. Zeros

are

placed into

the

high-order

end

of

the

even-numbered

register.

192

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