RCA 70/46 - Branching Instructions; Instruction Formats

BRANCHING
INSTRUCTIONS
INTRODUCTION
SEQUENTIAL
EXECUTION
INSTRUCTION
FORMATS
RS Format
Description
• In normal processor operation, instructions are executed in sequential
order according to the main memory locations in which they are stored.
When
branching is performed, a break in this normal sequential execution
occurs.
Branching instructions provide for referencing another subroutine
or repeating a segment of coding or continuing to the next instruction
in sequence. When branching occurs, the address specified in the branch
instruction replaces the current address in the P counter. The branch
address can be specified by an instruction address or it can be obtained
from one of the general registers.
The actual branching execution is based on the setting of the condition
code
or on the contents of a general register as specified in the loop-closing
operations.
In a branching operation, the current address in the updated P counter
can be stored before the branch address is placed in the P counter. This
stored address can be used for linking the new segment of instructions
with the segment of instructions from which the branching occurred.
The Execute instruction is listed with the branch instructions, although
only a
temporary departure from sequential operation is entailed by use
of this instruction. The branch address, in this instruction, specifies one
instruction to be executed in the instruction sequence. The address in the
P counter is not replaced by the branch address and only the instruction
located at the address is executed before the sequence is continued based
upon
the updated P counter.
• Normally, the P counter instruction address specifies a main memory
location
from which the next instruction to be executed is fetched. This
instruction address is updated in the P counter by the length, in bytes, of
the instruction to be executed as indicated by the current P counter. The
instruction currently indicated by the P counter is executed and the opera-
tion is repeated using the updated P counter to fetch the next instruction.
Instructions can occupy from one halfword (two bytes) up to three
halfwords (six bytes). The high-order two bits of the operation code of
each instruction designates its length as follows:
00 = halfword instruction (two bytes).
01, 10 = two-halfword instructions (four bytes).
11 = three-halfword instructions (six bytes).
• Branching instructions use the following three instruction formats:
o
7 8 11 12 15 16 19 20 31
• The contents of the general register specified by B2 are added to the
contents of the D2 field to obtain the branch address (second operand).
The Rl field specifies the general register that contains the first operand.
The R3 field specifies the general register that contains the third operand.
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