RCA 70/46 - Shift Left Single Logical (SLL)

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Shift Left Single

Logical

(SLL)

General Description

Format

(RS)

Condition Code

Interrupt Action

Notes

Logical

Instructions

•

The

entire

contents

of

the

general

register

specified

by

the

first

address

(R

1

)

are

shifted

left

the

number

of

bit

positions specified by

the

second

address

(B

2

/D

2

).

The

R3

field is ignored.

The

second

address

does

not

refer

to a

main

memory location. The low-

order

six

bits

of

the

second

address

are

used

as

the

count

to

specify

the

number

of

bits

of

shifting

to be done. The

remaining

bits

are

ignored.

89

o 7 8 11 12 15 16 19

20

31

• Unchanged.

•

None.

• 1.

High-order

bits

of

the

register

are

shifted

out

and

lost.

2. Zeros

are

placed into

the

right

end

of

the

register.

3. All 32

bits

of

the

specified

register

are

shifted.

189

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