RCA 70/46 - Shift Left Double Logical (SLDL)

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Shift Left Double

Logical

(SLDL)

General

Description

Format

(RS)

Condition Code

Interrupt

Action

Notes

Logical

Instructions

• The

entire

contents

of

the

double-length operand

(two

general

registers)

- even/odd specified by

the

first

address

(Rd

are

shifted

left

the

number

of

bit

positions specified by

the

second

address

(B

2

/D

2

).

The

R3

field

is ignored.

The

second

address

does

not

refer

to

a

main

memory location.

The

low-

order

six

bits

of

the

second

address

are

used

as

the

count to specify

the

number

of

bits

of

shifting

to be done.

The

remaining

bits

are

ignored.

0

•

•

•

8D

I

Rl

I

R3

I

B2

I

D2

7 8

11

12

15

16

19

20

31

Unchanged.

Address

error:

l.

2.

3.

4.

Specification.

The first

address

must

specify

an

even-numbered

register.

All

64

bits

of

the

double-length operand

are

shifted.

High-order

bits

are

shifted

out

and

lost.

Zeros

are

placed into

the

low-order end

of

the

odd-numbered

register.

191

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