Program
Interrupt
Block
2 •
If
the
interrupt
condition is one of the above, the
program
mask
(machine register)
for
the
current
program
state
is checked to see
if
the
interrupt
is permitted.
If
the
program
mask indicates
that
the
interrupt
is inhibited
(mask
=
0),
the
interrupt
condition is cancelled
and
the
next
instruction in the
current
processor
state
is executed.
Block
3 •
If
the
interrupt
condition is not one of the
four
program
interrupts,
or
is one of the
four
program
interrupts
but
the
program
mask
indicates
that
the
interrupt
is to be permitted
(mask
=
1),
the specific
bit
associated
with
the
interrupt
condition is
set
in
the
Interrupt
Flag
register.
Block
4 • The
bit
in the
Interrupt
Flag
register
is compared with
the
correspond-
ing
bit
ill the
Interrupt
Mask register
for
the
current
state.
If
the
bit
in
the
Interrupt
Mask
register
is reset
(0),
the
interrupt
condition remains
pending
and
the next instruction in the
current
processor
state
is executed.
The
interrupt
remains pending until the
mask
is changed to a
permit
status
and
the
interrupt
is serviced.
Block
5 •
If
the
bit
in the
Interrupt
Mask
register
is set, the
interrupt
is
taken
and
information OLC,
CC,
program
mask) is stored in
the
P counter
of
the
state
being terminated.
Blocks
6
and
7 •
If
the
interrupt
condition is a power failure, a machine check,
or
Scratch
Pad
Memory
parity
(if
applicable),
the
Machine Condition
State
P 4 is initiated. The flag in the
Interrupt
Flag
register
is reset.
Block
8 •
If
the
interrupt
is a Machine Check, the
Program
Indicators
are
stored
in
the
Interrupt
Status
register
of P
4'
Block
9 •
If
the
interrupt
condition is not a power failure
or
machine check,
the
Interrupt
Control
State
P
3
is initiated.
The
flag
in
the
Interrupt
Flag
register
is reset.
Block
10
• The condition code
setting
and
the
program
mask
are
extracted
from
the
P counter
of
the initiated
state
and
stored in
the
appropriate
hardware
registers.
Block
11 • The memory protection key, the decimal code
and
the
privileged mode
bits
are
extracted from the
Interrupt
Status
register
of
the initiated
state
and
stored
in
the
appropriate
registers.
Block
12
• The
state
being terminated is identified to
the
state
being initiated by
setting
an
interrupted
state
identifier code in
the
Interrupt
Status
register
of the initiated state.
Block
13
• The weight of
the
condition causing the
interrupt
is stored
in
general
register
No. 15
of
the initiated
state
(P
3
or
P
4
).
32
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