Channel Command
Word (CCW)
(Cont'd)
Input/Output
Operation
mand
word
designates
an
area
of
main
memory
at
which to continue
the
current
operation. When one channel command
word
has
a lapsed
byte
count,
the
next
channel command word in sequence is auto-
matically fetched. The
current
operation is continued
at
the
main
memory
area
specified by
the
new channel command word. The
command code
of
the
new CCW is ignored unless
it
specifies a
Transfer
in
Channel.
If
any
of
the
following channel
status
byte
conditions occur,
the
chain is
terminated
(see Channel
Status
Byte
for
further
definition) :
Program
Check
Protection Check
Channel Control Check
Channel
Data
Check
(if
the
operation is a
write)
Incorrect
Length
Condition
When
data
chaining, the chain
data
flag in
the
last
channel command
word
must
be reset. This causes
the
data
chain
to
be
terminated
upon completion
of
the
operation
specified by
this
CCW.
2.
Bit
position 33 is
the
Chain Command flag
(CC).
The
70/46
Proces-
sor
can
perform
several operations to
an
input/output
device
by
executing one
Start
Device instruction. When command chaining is
specified
by
setting
this
bit, a chain (series of channel command
words in sequence) is used and each channel command
word
specifies
the
operation to be performed. When
the
operation specified
by
one
channel command word is completed, the
next
channel command
word
in sequence is automatically fetched
and
the
operation specified
is initiated.
If
any
of
the
following conditions occur,
the
chain is
terminated:
a. Channel
status
byte conditions (see channel
status
byte
for
further
definition).
Incorrect
Length
Condition
and
suppress
length flag is zero.
Program
Check
Protection
Check
Channel Control Check
b.
Standard
device byte conditions (see
standard
device byte
for
further
definition).
Secondary
Indicator
is
set
Device Inoperable is
set
Device
End
is
not
set
When command chaining,
the
chain command flag in
the
last
channel
command word
must
be reset. This causes
the
command chain
to
be
terminated
upon completion of
the
operation specified by
this
CCW.
3.
Bit
position 34 is
the
Suppress
Length
Indication flag
(SLI).
Incor-
rect
length
occurs
in
the
70/46
Processor
when
the
number
of
bytes specified in
the
channel command word is not equal to
the
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