CompactFlash Memory Card Product Manual
SanDisk CompactFlash Memory Card Product Manual © 1998 SANDISK CORPORATION4
Table of Contents (continued)
4.3.5 Interface/Bus Timing..........................................................................................30
4.3.6 Attribute Memory Read Timing Specification.....................................................30
4.3.7 Attribute Memory Write Timing Specification....................................................31
4.3.8 Common Memory Read Timing Specification.......................................................32
4.3.9 Common Memory Write Timing Specification......................................................33
4.3.10 I/O Input (Read) Timing Specification................................................................34
4.3.11 I/O Output (Write) Timing Specification............................................................35
4.3.12 True IDE Mode I/O Input (Read) Timing Specification.........................................36
4.3.13 True IDE Mode I/O Output (Write) Timing Specification.....................................37
4.4 Card Configuration........................................................................................................38
4.4.1 Attribute Memory Function.................................................................................39
4.4.2 Configuration Option Register (Address 200h in Attribute Memory).....................40
4.4.3 Card Configuration and Status Register (Address 202h in Attribute Memory).......40
4.4.4 Pin Replacement Register (Address 204h in Attribute Memory)............................41
4.4.5 Socket and Copy Register (Address 206h in Attribute Memory)............................42
4.5 I/O Transfer Function.....................................................................................................43
4.5.1 I/O Function.......................................................................................................43
4.6 Common Memory Transfer Function.................................................................................44
4.6.1 Common Memory Function...................................................................................44
4.7 True IDE Mode I/O Transfer Function..............................................................................45
4.7.1 True IDE Mode I/O Function................................................................................45
5.0 ATA Drive Register Set Definition and Protocol..................................................46
5.1 I/O Primary and Secondary Address Configurations........................................................47
5.2 Contiguous I/O Mapped Addressing................................................................................48
5.3 Memory Mapped Addressing..........................................................................................49
5.4 True IDE Mode Addressing..............................................................................................50
5.5 ATA Registers................................................................................................................51
5.5.1 Data Register (Address - 1F0[170]; Offset 0,8,9)...................................................51
5.5.2 Error Register (Address - 1F1[171]; Offset 1, 0Dh Read Only)...............................52
5.5.3 Feature Register (Address - 1F1[171]; Offset 1, 0Dh Write Only)..........................52
5.5.4 Sector Count Register (Address - 1F2[172]; Offset 2).............................................52
5.5.5 Sector Number (LBA 7-0) Register (Address - 1F3[173]; Offset 3)..........................52
5.5.6 Cylinder Low (LBA 15-8) Register (Address - 1F4[174]; Offset 4).........................52
5.5.7 Cylinder High (LBA 23-16) Register (Address - 1F5[175]; Offset 5)......................52
5.5.8 Drive/Head (LBA 27-24) Register (Address 1F6[176]; Offset 6)............................53
5.5.9 Status & Alternate Status Registers (Address 1F7[177]&3F6[376]; Offsets 7 & Eh) 54
5.5.10 Device Control Register (Address - 3F6[376]; Offset Eh).......................................54
5.5.11 Card (Drive) Address Register (Address 3F7[377]; Offset Fh)..............................55
6.0 ATA Command Description .........................................................................56
6.1 ATA Command Set.........................................................................................................56
6.1.1 Check Power Mode - 98H, E5H............................................................................58
6.1.2 Execute Drive Diagnostic - 90H...........................................................................58
6.1.3 Erase Sector(s) - C0H..........................................................................................59
6.1.4 Format Track - 50H............................................................................................60
6.1.5 Identify Drive - ECH.........................................................................................60
To Next Page
Loading...
Need help?
General