B-1
S7-200 Programmable Controller, CPU 210
C79000-G7076-C235-01
Special Memory (SM)
The bits of the SM memory not only provide a variety of status and control functions, but also
serve as a means of communicating information between the CPU 210 and your program.
You can read the special memory as bits or words. The program development station
(PDS 210) provides additional words of special memory for diagnostic capabilities.
SMW0: Status Bits
As described in Table B-1, the bits of SMW0 contain status bits that are updated by the
CPU 210 at the end of each scan cycle.
Table B-1 Special Memory Bits SM0.0 to SM1.7
SM Bits
Description
SM0.0 This bit is always on.
SM0.1 This bit is on for the first scan.
SM0.2 Reserved
SM0.3 Reserved
SM0.4 This bit provides a clock pulse that is off for 30 seconds and on for 30 seconds, for a
cycle time of 1 minute. It provides an easy-to-use delay, or a 1-minute clock pulse.
SM0.5 This bit provides a clock pulse that is off for 0.5 seconds and then on for 0.5 seconds
for a cycle time of 1 second. It provides either an easy-to-use delay or a 1-second clock
pulse.
SM0.6 This bit is a scan clock which is off for one scan and then on for the next scan. This bit
can be used as a scan counter input.
SM0.7 Reserved
SM1.0 This bit is turned on by the execution of the Increment Word or the Decrement Word
instructions when the result of the operation is zero.
SM1.1 This bit is turned on by the execution of the Increment Word or the Decrement Word
instructions when an overflow results.
SM1.2 This bit is turned on by the execution of the Increment Word or the Decrement Word
instructions when the operation performed produces a negative result.
SM1.3 Reserved
SM1.4 Reserved
SM1.5 Reserved
SM1.6 Reserved
SM1.7 Reserved
B
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