Index-5
S7-200 Programmable Controller, CPU 210
C79000-G7076-C235-01
Input simulator
order number, F-1
specifications, A-15
Inputs, basic operation, 4-4
Inserting an instruction, 3-16–3-20
Inserting and deleting rows
in a Status Chart, 2-15
in a Symbol Table, 2-14
Installation
agency certifications and specifications, A-3
clearance requirements, 1-4
considerations for installing a CPU 210
clearance requirements, 1-4
using DIN rail stops, 1-6
dimensions
CPU 210, 1-5
DIN rail, 1-5
PDS 210, 1-5
in a panel box, 1-7
on a DIN rail, 1-6
on a panel, 1-6
screw size, 1-6
setting the baud rate (PDS 210), 2-3
STEP 7-Micro/WIN
Windows 3.1, 2-2
Windows 95, 2-2
Instructions
And (A) / And Not (AN), 5-3
effect on the logic stack, 4-10, 5-3
And Load (ALD), 5-13
effect on logic stack, 5-13
Compare Word, 5-4
Contacts, 5-3–5-4
Counter (CTUD), 5-8
Decrement Word (DECW), 5-9
Disable Interrupt (DISI), 5-14–5-17
Enable Interrupt (ENI), 5-14–5-17
End, 5-11
End (MEND), 4-5, 5-11
execution times, E-1
Increment Word (INCW), 5-9
Interrupt, 5-14–5-16
Interrupt Routine (INT), 5-14–5-17
Jump to Label, 5-12
Load (LD) / Load Not (LDN), 5-3
effect on the logic stack, 4-10, 5-3
Logic Stack, 5-13
Move Word (MOVW), 5-10
Negative Transition (ED), 5-3
Normally Open / Normally Closed contact, 5-3
NOT, 5-3
On-Delay Timer, 5-6
Or (O) / Or Not (ON), 5-3
effect on the logic stack, 4-10, 5-3
Or Load (OLD), 5-13
effect on logic stack, 5-13
Outputs, 5-5
Positive Transition (EU), 5-3
Program Control, 5-11–5-12
Reset (R), 5-5
Return from Interrupt (RETI), 4-5, 5-14–5-17
Set (S), 5-5
standard contacts, 5-3
Timer, 5-6–5-7
Unconditional End (MEND), 4-5
Up/Down Counter (CTUD), 5-8
Watchdog Reset (WDR), 5-11–5-13
Interrupt instructions, 5-14–5-16
Disable Interrupt (DISI), 5-14–5-17
Enable Interrupt (ENI), 5-14–5-17
example, 5-16
Interrupt Routine (INT), 5-14–5-17
Return from Interrupt (RETI), 5-14–5-17
Interrupt Routine (INT) instruction, 5-14–5-17
Interrupts
effect on the Watchdog Reset (WDR)
instruction, 5-11
enabling and disabling, 5-14
example, 4-14–4-16, 5-16
guidelines and restrictions, 5-15
hardware interrupt, 4-5
affecting the scan cycle, 4-6–4-9
high-speed counter, 4-14–4-16, 5-16
instructions, 5-14
Interrupt instructions, 5-14–5-16
response time, 1-3
CPU 210 AC/AC/Relay, A-8
CPU 210 AC/DC/Relay, A-6
CPU 210 DC/DC/DC, A-4
PDS 210, A-10
sample interrupt routine, 4-14–4-16, 5-16
sharing data between main program and
interrupt, 5-15
system support, 5-15
Isolated DC wiring guidelines, 1-10
J
Jump to Label instruction, 5-12
K
Keyword, “network”, 2-8
Index
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