Cycle and reaction times
5.6 Sample calculations
CPU 31xC and CPU 31x, Technical data
5-26 Manual, Edition 08/2004, A5E00105475-05
Calculating the physical cycle time
Under consideration of communication load:
12.5 ms * 100 / (100-40) = 20.8 ms.
Thus, under consideration of time-sharing factors, the actual cycle time is 21 ms.
Calculation of the longest response time
• Longest response time = 21 ms * 2 = 42 ms.
• I/O delay
– The maximum delay of the input digital module SM 321; DI 32 x 24 VDC is 4.8 ms per
channel.
– The output delay of the digital output module SM 322; DO 16 x 24 VDC/0.5 A can be
neglected.
– The analog input module SM 331; AI 8 x 12 bit was configured for an interference
suppression at 50 Hz. The result is a conversion time of 22 ms per channel. With the
eight active channels, the result is a cycle time of 176 ms for the analog input module.
– The analog output module SM 332; AO 4 x 12-bit was programmed for the measuring
range of 0 ...10 Hz. This gives a conversion time of 0.8 ms per channel. Since
4 channels are active, the result is a cycle time of 3.2 ms. A settling time of 0.1 ms for
a resistive load must be added to this value. The result is a response time of 3.3 ms
for an analog output.
• Neither PROFIBUS DP, nor PROFINET IO are being used, so you do not have to make
allowances for any DP cycle times on PROFIBUS DP or for PROFINET IO update times.
• Response times plus I/O delay:
– Case 1: An output channel of the digital output module is set when a signal is received
at the digital input. The result is a response time of:
Response time = 42 ms + 4.8 ms = 46.8 ms.
– Case 2: An analog value is fetched, and an analog value is output. The result is a
response time of:
Longest response time = 42 ms + 176 ms + 3.3 ms = 221.3 ms.
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