Sony HBD-DZ950 - Page 35

DAV-DZ350/DZ650/DZ950
35
• IC Block Diagrams
– MAIN Board –
IC101 AM5888
VINFC
1
TRB1
2
REGO2
3
VINSL+ 4
REGO1
5
FWD
6
REV
7
VCC1
VCC2
8
VOTR–
9
VOTR+
10
VOSL+
11
VOSL–
12
VOFC–
13
VOFC+
14
MUTE
28
BIAS
27
TRB2
25
NC
24
VINLD
23
GND
22
VCTL21
NC
20
VCC2
19
VOLD–
18
VOLD+
17
VOTK–
16
VOTK+15
+

+

+

+

+

ACTUATOR
DRIVER (6x)
VCC1
VCC1
SLED
DRIVER (4x)
TRAY
DRIVER
MUTE
PRE
DRIVER
+

VCC2
ACTUATOR
DRIVER (6x)
THERMAL
SHUT DOWN
VCC2
SPINDLE
DRIVER (4x)
VCC2
VINTK
26
IC300 SDRAM 64M
DQ6 11
VSSQ
12
VDD
14
VDD
1
LDQM
15
DQ7 13
WE#
16
CAS#
17
RAS#
18
CS#
19
BA0
20
BA1
21
A
10/AP
22
A0
23
A1
24
A2
25
VDD
27
A3
26
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
COLUMN
COUNTER
ADDRESS
BUFFER
MODE
REGISTER
REFRESH
COUNTER
VSS
54
DQ13
50
DQ14
DQ15
51
53
DQ1147
DQ12
48
VDDQ
49
VSSQ46
VSSQ52
DQ10
45
DQ9
44
VDDQ
43
DQ8
42
A11
35
NC
36
CKE
CLK
37
38
A8
A9
33
34
A7
32
A6
31
A5
30
A4
29
VSS
28
UDQM39
NC/RFU
40
VSS
41
1M u 16
CELL ARRAY
(BANK #A)
COLUMN DECODER
DECODER
1M u 16
CELL ARRAY
(BANK #B)
COLUMN DECODER
DECODER
1M u 16
CELL ARRAY
(BANK #C)
COLUMN DECODER
DECODER
1M u 16
CELL ARRAY
(BANK #D)
COLUMN DECODER
DECODER
CLOCK
BUFFER
DQ
BUFFER
DQ5 10
DQ2 5
VSSQ
6
DQ1 4
DQ4 8
VDDQ
9
DQ0 2
VDDQ
3
DQ3 7