SOYO SY-7VBA133U - Page 69

BIOS Setup Utility
SY-7VBA133U
65
CHIPSET FEATURES SETUP (Continued)
CHIPSET
FEATURES
Setting Description Note
Disabled
PCI Master 0
WS Write
Enabled When Enabled, writes to the PCI
bus are executed with zero wait
states.
Default
Disabled
PCI Delay
Transaction
Enabled
The chipset has an embedded 32-bit
posted write buffer to support delay
transactions cycles. Select Enabled
to support compliance with PCI
specification version 2.1.
Default
Disabled
PCI#2 Access
#1 Retry
Enabled
When disabled, PCI#2 will not be
disconnected until access finishes
(difault). When enabled, PCI#2 will
be disconnected if max retries are
attempted without success.
Default
Disabled Default
AGP Master 1
WS Write
Enabled When
Enabled,
writes to the
AGP(Accelerated Graphics Port) are
executed with one wait states.
Disabled Default
AGP Master 1
WS Read
Enabled When Enabled, read to the AGP
(Accelerated Graphics Port) are
executed with one wait states.
Disabled Default
Memory
Parity/ECC
Check
Enabled This item enabled to detect the
memory parity and Error Checking
& Correcting.