8.5 Debug and bridge performance
Table 14 gives an overview of the achievable maximal performances with
STLINK-V3PWR on different
communication channels. Those performances are also depending on the overall system context (target
included), so they are not guaranteed to be always reachable. For instance, a noisy environment or connection
quality can impact system performance.
Table 14. Debug and bridge performances
Target
voltage
(T_VCC)
Data interface maximum frequency (in MHz)
SWD JTAG SWV VCP SPI
I
2
C
CAN
3.3 V
10 20 12 12 24 1 1
1.8 V 10 12.5 10 10 12 1 1
UM3097
Debug and bridge performance
UM3097 - Rev 1
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