Connecting to the board AN4989
42/118 AN4989 Rev 3
Especially since JTAG is using more pins, users should be aware that it is at the expense of
using some IPs.
Refer to the product datasheet for a detailed presentation of the default and alternative
function mapping for each pin.
4.2 Reset and connection mode
This section reviews the reset and connection mode available while using ST-LINK/V2or
STLINK/V3 debug interface.
4.2.1 Presentation
Connection mode and reset mode are 2 different but dependent concepts:
Reset mode can be either:
• Hardware: drive the NRST pin of the MCU. In all STMicroelectronics hardware kits, the
debugger can drive this NRST through ST-LINK/V2 or ST-LINK-V3.
Hint: On Nucleo, check that relevant Solder Bridge SB12 is not OFF.
• Software (write to core register)
– System: Core and all Peripheral SOC IPs are reset
– Core: Only Arm
®
Cortex
®
is reset
Connection mode can be either:
• Normal: Debugger takes control through JTAG/SWD port and starts execution after a
software reset.
This is working only if JTAG/SWD is available:
– GPIO correctly configured and clocked
– FCLK or HCLK enabled
– Main Power domain or Low-Power debug active
• ConnectUnderReset: Debugger takes control while asserted NRST pin, setting GPIO
and clock into there default state.
This is required in case of a reconnection to a system in Low-Power mode or which has
changed SWD pin to alternate functions.
• Hotplug: Debugger connect without reset nor halt. Once connected, the user can chose
to perform the required action (typically halt to get where the program stands and read
registers or memory for instance).
Reset and Connection mode are differently accessible and exposed depending on tool and
IDE.
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