Chapter 2: Installation
2-15
PRESS FIT
J*
MH15
MH14
MH13
MH12
MH11
MH10
S12
JTBT
B1
JBT1
U6
JSTBY1
SP1
JD1
JF1
JSD1
FAN5
FAN1
FAN4
FAN2
FAN3
S8
JTPM1
JPW1
LED3
A
C
LED2
LED1
JPW2
JL2
JSPDIF_OUT
JI2C2
JI2C1
JL1
LED4
JPAC1
JPL2
JBR1
JVR1
JLED1
JPL1
JWD1
JPME2
DESIGNED IN USA
C7Z270-PG
REV:1.00
BIOS LICENSE
MAC CODE
BAR CODE
2
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
LAN2
LAN1
ON
PWR
RST
XOH/FF
NIC
NIC
1LED
HDD
LED
PWR
OFF:DISABLE
ON :ENABLE
JI2C1/JI2C2
AUDIO FP
3 PIN POWER LED
JLED1:
ON:BIOS RECOVERY
COM1
JTPM1:
TPM/PORT80
OFF:NORMAL
JBR1
JL1:
CHASSIS
INTRUSION
USB6/7
USB4/5
USB2/3
USB 14/15 (3.0)
PCIE M.2 CONNECTOR 1
CPU SLOT1 PCI-E 3.0 X8 (IN X16)
1-2:RST
2-3:NMI
WATCH DOG
JWD1:
CPU SLOT3 PCI-E 3.0 X16
U.2 CONNECTOR 1
U.2 CONNECTOR 2
I-SATA4
I-SATA5
BUZZER:3-4
JD1:
SPEAKER:1-4
PCH SLOT4 PCI-E 3.0 X4
I-SATA2
I-SATA3
2-3:ME MANUFACTURING MODE
1-2:NORMAL
JPME2:
CPU SLOT5 PCI-E 3.0 X8 (IN X 16)
1-2:ENABLE
2-3:DISABLE
JPAC1:AUDIO
I-SATA0
I-SATA1
CPU SLOT7 PCI-E 3.0 X16
SYS_FAN2
PCIE M.2 CONNECTOR 2
SYS_FAN3
HD AUDIO
USB 12/13 (3.1)
USB 10/11(3.1)
2-3:DISABLE
JPL1:LAN1
1-2:ENABLE
USB8/9(3.0)
POWER BUTTON
DIMMB1
DIMMB2
DIMMA1
DIMMA2
HDMI/DP
RESET BUTTON
KB/MOUSE USB 0/1
SYS_FAN1
CPU_FAN1
CLEAR CMOS
CPU_FAN2
CPU
A. Back panel USB 2.0 #0
B. Back panel USB 2.0 #1
C. Back panel USB 3.1 #8
D. Back panel USB 3.1 #9
E. Back panel USB 3.1 #10
F. Back panel USB 3.1 #11
G. USB 2.0 Header #2/3
H. USB 2.0 Header #4/5
I. USB 2.0 Header #6/7
J. Back panel USB 3.0 #12/13
K. USB 3.0 Header #14/15
Universal Serial Bus (USB)
Two Universal Serial Bus 2.0 ports (#0/1), two USB 3.0 ports (#8/9),
four USB 3.1 ports (#10/11/12/13) are located on the I/O back panel.
In addition, one USB 3.0 header (two ports: #14/15), three USB 2.0
headers (six ports: #2/3, 4/5, 6/7) are also located on the motherboard
to provide front chassis access using USB cables (not included). See the
tables below for pin denitions.
Back Panel USB (2.0) #0/1, USB (3.1)
#8/9/10/11 Pin Denitions
Pin# Denition Pin# Denition
1 +5V 5 +5V
2 USB_PN1 6 USB_PN0
3 USB_PP1 7 USB_PP0
4 Ground 8 Ground
Front Panel USB (2.0) Header
#2/3/4/5/6/7 Pin Denitions
Pin # Denition Pin # Denition
1 +5V 2 +5V
3 USB_PN2 4 USB_PN3
5 USB_PP2 6 USB_PP3
7 Ground 8 Ground
9 Key 10 Ground
Front Panel USB (3.0) Header #12/13
Pin Denitions
Pin# Pin# Signal Name Description
1 10 VBUS Power
2 11 D- USB 2.0 Differential Pair
3 12 D+
4 13 Ground Ground of PWR Return
5 14 StdA_SSRX- SuperSpeed Receiver
6 15 StdA_SSRX+ Differential Pair
7 16 GND_DRAIN Ground for Signal Return
8 17 StdA_SSTX- SuperSpeed Transmitter
9 18 StdA_SSTX+ Differential Pair
G
H
I
J
A
B
C
D
E
F
K
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