TB8100 Installation and Operation Manual Functional Description 47
© Tait Electronics Limited June 2005
Receiver Path
On the receiver side, an RF input signal is received via the RF input BNC
connector, filtered, amplified then mixed down to the IF frequency. The IF
signal is further filtered and then transferred from the RF to the digital board
via a coaxial interconnection cable. On the digital board the IF signal is then
sampled and further sample-rate-reduced by the DDC. The DSP then
demodulates the signal and generates RSSI, SINAD and sub-audible
signalling values and passes these to the RISC. The demodulated signal is
then split and processed using the configured options as set by the user for
Path A & Path B responses. The Rx crosspoint switch patches the recovered
audio signals to the correct output paths, reflecting the current status of the
receiver.
The final received signal is then set to CODECs which convert the digital
signal back to audio. The system interface board provides level adjustments
and final output impedance buffering. The signal finally appears as audio
signals on the rear panel interface connector.
Transmit Path Audio signals presented to the system interface connector on the system
interface board are buffered and level-converted based on the user input gain
settings. These signals are then passed to the digital board and digitized via
the CODECs, read into the DSP, and passed to the Tx crosspoint switch.
Microphone audio is passed into the Tx crosspoint switch from the control
panel via the system control bus. Based on the current base station status,
the different audio inputs can be fed into either path A or B, which are then
further processed depending on the user-configured path options. Audio
from both paths is then added together and processed via the channel
limiter/low pass filter. This signal then has any sub-audible signalling added
to it that is needed for the active channel before it is sent to the FCL
(Frequency Control Loop). The FCL performs a dual point modulation
process to modulate the VCXO and exciter VCO simultaneously. The final
modulated carrier signal is then buffered and passed, along with the DC
PA_KEY signal, to the PA (Power Amplifier) via an SMA interconnection
cable.
The PA detects and keys the PA based on this DC signal, also amplifying the
+11dBm input signal from the reciter to the final RF output power, which
is determined by the current channel output power setting. The amplified
RF output signal is then processed through a harmonic filter and a
directional coupler. The direction coupler provides power level information
to the PA to monitor and respond to the VSWR conditions on the PA
output.
Clock Processing The reciter reference clock can be selected from an external or internal
source (external reference or internal TCXO). Once the clock source has
been selected (based on the configuration and current operating status of the
base station), the 12.8MHz signal is passed from the RF board to the digital
board. On the digital board, the 12.8MHz signal is used by the CODECs,
and also generates the 40MHz clock for the DSP/RISC. This clock
structure ensures all clocks on the reciter are phase locked together to limit
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