Phase Comparator output 2 (PC2 OUT at pin 13) of
PLL U314, outputs the PLL ERROR signal whenever the
leading edges of the HORIZCLK signal on pin 3 and the
horizontal-sync pulses on pin 14 do not coincide. The error
signal output is integrated by R322, R320, and C322 to
produce a voltage (applied to pin 9) used to correct the
operating frequency of the VCO. When either no phase
errors exist or no signals are present to compare (both
phase-comparator inputs at the same level), pin 13 goes
to a high-impedance state, and the voltage on C322 main-
tains the operating frequency of the VCO. Resistors R323
and R324 and capacitor C324 set the operating frequency
range of the PLL circuit. A bleeder resistor, R327, reduces
the charge on C322 slightly between each error signal out-
put so that the HORIZCLK signal will always lag the
horizontal-sync of the input signal by a small amount. This
The 2XH VCO (voltage-controlled oscillator) output is
divided by two by flip-flop U220B to produce both the
HCLK and HORIZCLK signals at the horizontal-line rate.
Horizontal sync from the input signal is applied to the
Phase Comparator input of U314 at pin 14 via U308B. The
HORIZCLK from the
0
output of U220B is applied to
U314 at pin 3 through U308C.
PHASE-LOCKED LOOP (PLL). Phase-Locked Loop
U314 locks onto the horizontal-sync signal to produce a
synchronized clock at twice the horizontal-sync rate (2XH).
The 2XH clock is used to extract the various sync- and
field-identification signals from the composite-sync
waveform. It is also divided and delayed to obtain the
DLY'D HCLK (see Figure 3-13) signal used in eliminating
alternate equalizing and serration pulses from the HOR-
IZCLK signal and the input to the PLL Phase Comparator
inputs.
CLOCK FREE RUN. If non-NTSC standard television
signals are being used, the vertical-sync block may not be
serrated. To maintain the proper horizontal-sync rate dur-
ing the absence of signal-supplied horizontal pulses, the
Clock Free-Run circuit produces "artificial" clock pulses.
Therefore, the line count will continue and be correct when
the next horizontal-sync pulse does arrive. The signal used
as the self-generated HORIZCLK signal is derived from the
VCO (voltage-controlled oscillator) output (2XH) of the
Phase-Locked Loop circuit. That signal, at twice the
horizontal-sync rate, is divided by two at the
0
output of
flip-flop U220B. It is then wire-ORed into the HORIZCLK
signal line via R334 and CR332. If a horizontal-sync pulse
is not present to trigger the monostable multivibrator,
CR332 will be biased on by the HI HCLK to pass that
pulse to the HORIZCLK signal line. When the Phase-
Locked Loop (PLL) circuit is locked (synchronized) with the
incoming horizontal sync, the HCLK rising edge will slightly
lag the incoming sync pulse to prevent jitter of the HOR-
IZCLK signal to U524B.
3-84
Since the equalizing and serration pulses in the
vertical-sync block occur at twice the horizontal-sync rate
(see Figures 3-13 and 3-14), every other one must be
prevented from triggering the monostable multivibrator to
keep the line count correct. The DLY'D HCLK (delayed
Horizontal clock) applied to the base of U420B (via R210)
holds that transistor on for a period of time between the
normal horizontal line-sync pulses. This action effectively
removes the unwanted pulses from the HORIZCLK output
by preventing them from triggering the multivibrator circuit.
Transistors U420B, U420C, and associated com-
ponents form a monostable multivibrator used to stretch
the width of the horizontal-sync pulses. The leading edge
of each horizontal-sync pulse turns on U420C which, in
turn, reverse biases diode CR224 via C325 to turn off
U420B. The resulting HI at the collector of U420B keeps
U420C biased on (via R421). The output at the collector of
U420B remains HI until C325 charges to about + 1 volt via
R224; then, CR224 becomes forward biased to once again
turn U420B on. The collector voltage of transistor U420B
then drops to about + 0.4 V, at which point diode CR329
conducts to clamp the output at one diode drop above
ground. This stretched output pulse from the monostable
multivibrator is level-shifted down one diode drop through
CR328 to produce the TIL-compatible HORIZCLK signal
used to generate trigger signals to the main Trigger circuit
of the oscilloscope.
PULSE STRETCHER. The Pulse Stretcher lengthens
the horizontal-sync pulse width to produce a more sym-
metrical, faster rise-time clocking pulse. It also removes
alternate equalizing and serrated pulses that occur during
the NTSC TV signal vertical-sync block from the
composite-sync waveform in order to maintain the correct
horizontal clock rate.
Transconductance Amplifier U504 is enabled by turning
transistor U410A off on the falling (trailing) edge of the
inverted sync pulse from
0504
(via C308). Bias current to
turn on U504 is then supplied through R403. The amplifier
will stay enabled until the current supplied by resistor
R214 charges C308 back positive enough to bias U410A
back on (in approximately 1 us), During the time that U504
is enabled, it senses the back-porch level of the
composite-video waveform applied to pin 3 via resistive
divider R613, R602, and R604. Depending on whether the
sensed level is above or below the ground reference level
on pin 2, the amplifier output will either charge or
discharge capacitor C713 to a new voltage level. This will
slightly change the offset voltage applied to pin 4 of
U610B (via U710C), shifting the entire composite-video
waveform in the direction required to hold the back-porch
level at +4.5 volts (zero volts on pin 3 of U504). During
the period between back porches, C713 acts as a hold
capacitor to maintain the offset bias on U610B.
Theory of Operation-2430 Service
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