- 2 V Regulator
A - 2 V supply needed to terminate all of the high-
speed ECl signals on the Main circuit board is formed by
U580B and Q580. The circuit is a simple series-passregu-
lator with R585 and R586 developingthe -2 V reference
for operational amplifier U580B from the- 5 V supply.
Feedbackis through R587. Collector load resistors R486,
R487, and R488 limit the power dissipation of 0580 and
protect it from possibleshort circuits of the -2 V supply.
RESETDRIVER.This driver consistingof 0551 is ident-
ical to the C Clock Driver states. It takes the RESETsig-
nal input from U731C in the System Clocks circuitry
(diagram7). Like the C Clock Drivers, the Reset driver is
driven HI during Fast-in and toggles at other times. The
Reset driver output is held HI for only 200 ns of the 2
J.LS
clock period.
"C" CLOCK DRIVERS.These are external clock drivers
consisting of 0450, Q550, Q460, 0560, and associated
components. They provide the necessary - 5 V to+ 5 V
clock swings for the CCD"C" register gates. Each driver
is simply an inverting buffer which acceptsTTL inputs from
the Phase Clock Array. During the Fast-In portion of the
FISO acquisition cycle, the outputs of all four drivers are
held HI by the Phase Clock Array. During the Slow-Out
portion of the cycle, and at SEC/DIV settings of 100
J.LS
and slower, the C Clock Drivers toggle at a 500 kHz rate
in the normalfour-phasesequence.
Resistor array R470 provides proper termination for the
ECl logic inputs to the CH 1 Clock Drivers.
Since the B register drivers have totem-pole outputs
with emitter-followers for pull-ups, their HI state outputs
are reduced from the+ 5 V supply by approximately 1 V.
Resistors R466, R465, R366, and R365 reduce the tran-
sient current flow into the B register gates when the B
drivers changestate.
Each Clock Driver integrated circuit has only two B
register drivers. Therefore, the B register drive task is
shared between the two CCD/Clock Driver hybrids. The
Clock Drivers in U450 drive the 1Band 3B gates of both
CCD arrays, and the ones in U350 drive the 2B and 4B
gates of both CCD arrays (seediagram 10). The Transfer
Out (TO) gate timing has to match the 4B gate timing;
therefore, the TO gate inputs of each CCD are tied to the
4B gate signalthrough R345.
the clocks then are set to approximatelythe-5 V supply
level. Bias stability is thereby maintainedover temperature
and componentvariations.
3-48
Channel 1 CCD bias current for the high-speeddrivers
is set by the feedback circuit of U360A and Q375. The
drivers are biased by injecting current into the IS input
(pin 29). Increasingthe current makes the lO level of the
high-speedclocks more negative; decreasing the current
raises the lO level. The HI level of the clocks is always
within a few hundred millivolts of the+5 V supply to the
hybrid. For controlling the negative clock level, the
common-modelevel of the 1A and 3A clocks at the P1A
and P3A outputs is applied to the input of U360A. This
level is compared to the midpoint between the+ 5 V and
-5 V supplies. Operational amplifier U360A drives the
base of 0375 to a level such that the current injected into
IS sets the common-modelevel of P1A and P3A equal to
the voltage at pin 3 of U360A(the voltage supply midpoint
value). Since the HI clock levels at P1A and P3A are
approximately at the+5 V supply level, the lO levels of
The 1A and 3A high-speed clocks are accessible at
probe pins 21 and 20 of the hybrid devices. These pins
(P1A and P3A) are isolated from the actual CCD gates by
internal 875-ohm series resistors. Terminate the signals
into 50 ohms to view them. Using the standard 10 MQ
probe will cause the signals to have a displayed rise time
of about 30 ns; the actual rise time internally is
about 2 ns.
The Clock Driver integrated circuits internal to the
CCD/Clock Driver hybrids develop the four"A" register
clocks, the four "B" register clocks, the two sample
clocks, and the transfer input (TI) clock for the CCD. The
high-speed Sample A Register and TI drivers are
differentialclass A drivers through thick-film load resistors
on the hybrid. The B Register drivers are slower with
active pull-up and pull-down totem-pole outputs similar to
conventionalTTL driver outputs.
Clock Drivers
The output diffusions for sides 1 and 3 (001 and 003)
are independently driven from the DAC system. Varying
the voltages on these nodes varies the gain of the CCD.
These adjustments are used in conjunction with the
Common-Mode Adjustments to calibrate the gains of the
Peak Detector and CCD/Clock Driver subsystem. Gain
increases with increasing 00 voltage and decreasing
Common-mode voltage; therefore, the calibration firmware
moves these voltages in opposite directions to effect
calibration.
shifted serially through the CCD via one B register channel
only. The TI clock toggles continuously to move the sam-
ple charge packets from the first A register position into
the active B register channel, shown in Figure 3-5 as the
Short-Pipe (slow-in, slow-out) path.
Theory of Operation-2430 Service
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