3-49
Various strobes used for internal control of the Trigger
LogicArray may be generated.
The internal events and delay counter low-byte or high-
byte of the number of events to be counted or delay
may be loaded.
Mode control data may be loaded into the internal
mode register.
Oependingon the addresswritten to, one of the follow-
ing actions may occur:
The three enable inputs to U370, E1B (A3), E2B (WR),
and E3B (ACQSEL), are all set LO whenever writing to
addresses between 6080h and 6087h to enable the
address inputs (AO, A1, and A2). The choice of eight
addressesbetween6080h and 6087h providesfor different
operating requirementsof the Trigger Logic Array.
Trigger LogiC
The Trigger Logic circuit consists primarily of Trigger
Logic Array U370. The Trigger Logic Array provides final
trigger-source selection; trigger-point delays, delayed
either by a specified amount of time or by a specified
number of events; and ramp-control signals to the .ntter-
Correction circuitry for resolving trigger-point ambiguities.
The Trigger Logic Array also produces the trigger and
externalclock signals necessary to control operations of
the CCO PhaseClock circuit.
Each differential trigger gate is inverted and current
bufferedby a pair of differentialtransistors that allow quick
response to the trigger edges by Trigger Logic
Array U370.
When the definedtriggering criteria are met for either A
or B, the associated trigger outputs (ATG, ATG for A
Trigger; BTG, BTG for B Trigger) will go to their asserted
(true) states. The exception is when the A Trigger holdoff
has not finished (ATHO is still HI). When the holdoff ends,
however, the next trigger event on the selected A Trigger
input will assert the A Trigger output gates.
Control data from the System IlP definingtrigger mode,
trigger coupling,and trigger slope are clocked serially (one
bit at a time) from the CO (control data) line into two
storage registersinternal to U150. Clocking the CCA (con-
trol clock A) line moves the setup data to the A control
register, while clocking CCB moves data to the B control
register. When the control data has been loaded, each
trigger circuit beginscomparing its selectedinput signal to
the user-definedtrigger levelfor that trigger channel.
Theory of Operation-2430 Service
AlB Trigger Generator
The A/B Trigger Generator circuit, composed of U150
and associated components, provides for selection and
analog-type trigger detection from five input signals for
each of the A and B triggers. These are the CH 1 and
CH 2 verticalinputs, the EXT 1 and EXT2 trigger inputs,
and the line-triggerinput (Atrigger only).Two multiplexers
internal to U150 select one of these signals as the trigger
source for A Trigger and one (excluding the LINE signal)
for B Trigger. Source selection depends on the states of
the SROA, SR1A, and SR2A (source select-A trigger)
lines for the A Trigger and on SROB,SR1B, and SR2B for
B Trigger. The appropriate select bits are writteninto
register U140 by the System IlP whenever the operator
makes a triggering condition change using the trigger
sourcemenus.
The Phase Locked Loop and CCO PhaseClock circuits
(diagram11) control sampling and shifting operations of
the CCO/Clock Oriver hybrid. The Phase Locked Loop
synthesizes the 200/250 MHz sample clock driving the
CCO Phase Clock Array. The CCO Phase Clock Array
uses this "master" clock to generateother CCO clocks in
accordance with mode data writtento it from the
SystemIlP.
The Trigger circuits (diagram 11) detect when the user-
defined triggering conditions are met and then allow the
acquisitionto be completed.Whenthe triggering signallim-
its defined by the user for slope, level,and variableholdoff
are detected by A/B Trigger Generator U150,the resulting
trigger output is applied to Trigger Logic Array U370,
where triggering conditions of delay mode, delay time or
delay events count, and optional trigger sources are taken
into consideration.The Trigger Logic Array outputs several
trigger-recognition and acquisition-control signals that
cause the acquisition system to finish the "post-trigger"
portion of the acquisition.
In the 2430, the acquisition system continuously
acquires input samples. When the user-specified number
of "pretrigger" samples have been moved into the CCO
arrays, the trigger system is allowed to recognizetrigger
events. Sampling of the signal input to the CCO arrays
continues (with new samples pushing out old samples)
until a trigger occurs. After the trigger, the number of
"post-trigger" samples neededto fill the waveform record
are moved into the CCO arrays and samplingis stopped.
The acquired samples are then moved out of the CCO
arrays, digitized, stored to memory, and displayed. The
acquisition system then begins again to fill the"pretrigger
window" for the next acquisition;and, when that has been
done, the trigger system is enabled to look for the next
trigger event.
TRIGGERS AND PHASE CLOCKS
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