3-93
Primary Fault SenSing
Primary current, primary regulated voltage, and primary
unregulated voltage are monitored by circuitry to prevent
catastrophic failure. Should conditions arise that cause an
excessive primary current or an excessive primary regu-
lated voltage, limiting occurs. The excessive primary
current and primary regulated voltage functions share
much common circuitry, while the low unregulated primary
voltage circuitry is entirely independent of the first two
fault-sensing circuits.
A clock pulse from U233 is applied to a TTL-CMOS
level shifting buffer (U840D) at the beginning of every
switching cycle. The level-shifted clock pulse at the output
of U840 clocks U829B, a CMOS D-type flip-flop
(configured to toggle with each clock). The Inverter switch
transistors, Q521 and Q721, are alternately turned on and
off by the flip-flop outputs and are connected to opposite
ends of the primary winding of the output transformer.
Driving the inverter switches in alternate fashion produces
ac currents in the secondary windings of the output
transformer that are rectified, providing the various unreg-
ulated dc supply voltages.
INVERTER. The Inverter circuit alternately switches
current through each leg of the primary winding of output
transformer T639. The circuit is made up of Q521, Q721,
U840D, U829B, and associated components.
With a higher current applied to the transformer pri-
mary, higher voltages appear across the secondary wind-
ings of T639 with each cycle. This causes the secondary
voltages to return to their nominal levels. As the +5 VD
line returns to its nominal level, base drive to the shunt
transistor stabilizes at a level that keeps the sensed
+5 V
D
level in regulation. Should the FEEDBACK signal
level tend too high, opposite control responses occur.
Further information about the FEEDBACK signal is given
in the + 5 V Inverter Feedback description.
the +5 V Inverter Feedback amplifier (U189, diagram 23)
and is directly related to the level of the + 5 V
D
supply
line. If the FEEDBACK signal goes above its nominal level
(+5 V
D
is too low), base drive to the shunt transistor (in
optoisolator U155) increases. This increase causes addi-
tional current to be shunted around R144 (via R145 and
phototransistor of U155) and changes the ratio of the
sensing divider. The voltage at the center tap of T639
must increase to balance out the changed sense ratio and
maintain balance in the error amplifier. Since the output of
the error amplifier controls the current to the primary wind-
ing of the output transformer, and since the error amplifier
sensing depends on a balanced condition, the voltage at
the transformer primary increases.
Theory of Operation-2430 Service
Optoisolator U155 and resistor R145 form a control
network that allows a voltage sensed at the FEEDBACK
input to slightly alter the voltage-sense reference applied
to pin 1 of U233. The FEEDBACK signal is generated by
The lower of the two negative input levels determines
the actual negative comparison point of the PWM com-
parator; and this level determines the point at which the
positive-going ramp, applied to the positive input, switches
the PWM comparator to initiate the off state of the PWM
switch. The PWM series switch is turned on at the begin-
ning of each clock cycle; turn-off occurs when the
positive-going ramp crosses the threshold level of the
PWM comparator. The lower the level at the controlling
(negative) input, the shorter the PWM switch "on time."
Depending on the output level sensed, the duty cycle of
the drive signal changes (sensed level rises or falls with
respect to the triangular waveform applied to the positive
PWM comparator input) to hold the secondary supplies at
their proper levels.
PREREGULATION. Once the initial charging at power-
up is accomplished (as just described), the voltage-sensing
circuitry begins controlling the Inverter switching action.
The voltage level at the primary center tap of T639 is
divided by sense string R146-R144, and the resulting volt-
age is applied to the error amplifier internal to U233 at
pin 1. The + 5.1 V reference generated by U233 is applied
to pin 2 of U233, the other input of the error amplifier. If
the sensed level at pin 1 is lower than the reference level
at pin 2 (as it always is for the first few switching cycles),
the output of the error amplifier is high. This high level is
applied to a negative input of the PWM comparator; the
other negative input is applied from the soft-start capacitor
(described previously).
As the control power supply turns on, a 50 f.lA current
source internal to U233 begins to charge capacitor C128
positive. This charging level, applied to one of the negative
inputs of the PWM comparator, allows drive pulses of
greater and greater duty cycle to be generated. These
pulses drive the series switching transistors (Q421 and
Q423), and their slow progression from narrow to wide
causes the various secondary supplies to gradually build
up to their final operating levels. This slow buildup
prevents a turn-on current surge that would cause the
current-limit circuitry to shut down the supply.
PREREGULA TOR START -UP. As the supply for the
Preregulator control IC is established, an internal oscillator
begins to run. The oscillator generates a repetitive triangu-
lar wave (as shown in Figure 3-16) at a frequency deter-
mined primarily by R228 and C227 (with R227 having a
minor effect since it controls the discharge time of timing
capacitor C227).
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