3-95
At instrument turn-on, after the rectified line voltage
comes up, the control power supply begins supplying
power to the control circuitry. At that time, the output of
comparator U834 goes LO at pin 7 to turn on the LED in
optoisolator U265. This action biases on the output
transistor of the optoisolator and switches the LINE UP
LINE UP.
The Line Up circuit, composed of U834B,
U265,and associatedcomponents,sensesthe levelof the
rectified line voltage and relays its status through the
PWRUPcircuit to the System ILP.The signal from voltage
divider R325-R835is low-pass filtered by C835 and is
applied to the inverting input of comparator U834B. The
noninverting input of the comparator is referencedto the
+5.1 V referencefrom U233. The output of the compara-
tor drives the light-emittingdiode of optoisolator U265, so
whenever the rectified line-inputvoltage is below the nor-
mal operating level (approximately+ 178 V), the light-
emitting diode (LED) is off. With the LED off, the output
phototransistorof U265 is biasedoff.
Capacitor C829 is once again charged through R824
and CR824 with a relatively short time constant, allowing
U829A to be triggered again (if the fault persists) by the
time the Control Power Supply restarts.
Monostable U829A is designed to remain active long
enoughfor the Control Power supply to decay and discon-
nect. The disconnect level is approximately half of the
Control Power Supply voltage and, once disconnected,
supply voltage is reestablishedin 0.5 to 2 seconds. The
time it takes C244 to charge from the"disconnect thres-
hold" to the Control Power Supply"turn-on threshold" is
the dominate factor in determiningthe power supply res-
tarting time when recoveringfrom an over-currentor over-
voltagefault condition.
The high
0
output of U829A, connected to the
shutdown input to U233, turns off the PWM switch (Q421
and
0423)
immediatelyand keeps it off until
0
returns low
(when the Control Power Supply decays and turns U829
off). However, the PWM clock continues to run and the
Inverter switches (Q521 and Q721) continue to operate.
Since the PWM switch is not operating, energy is not
transferred to the Control Power Supply via T335, and
C244dischargesbelow the minimumvoltage level required
by the Control Power Supply circuit (through the normal
circuitload).When this minimumlevel is reached,the Con-
trol Power Supply regulator disconnectsfrom C244, inter-
rupting the power to the control circuitry and stopping the
Inverterswitches.
that the
0
output of U829A is held high long enough for
soft-start capacitor C128 and Control Power Supply capa-
citor C244to fully discharge.
Theory of Operation-2430 Service
Prior to being clocked, U829A (configuredas a mono-
stableflip-flop)is in a reset state with its Q output set low.
This is the normal operating mode and allows the series
switch to be controlled by the regulating functions of
U233. Capacitor C829 chargesto the Control Power Sup-
ply voltage via R824 and CR824 (diode CR824 shunts
R934 when charging C829 to provide a relatively fast
charging path). When the flip-flop is clocked (indicatinga
fault-sensefrom the voltage-or current-sensecircuits),the
Q output goes high and C829 beginsto discharge.With
0
high, CR824 becomesreversebiased so that dischargeof
C829 is through R934, providing a relatively slow
discharge compared to the charging time. This ensures
SHUTDOWNTIMER.
The ShutdownTimer ensuresthat
the preregulatorseries switch remainsoff long enoughfor
energy stored in C128 (the soft-start capacitor) and C244
(the Control Power Supply energy-storage capacitor) to
drain down via normal circuit loading should an over-
current or over-voltagefault occur. Shutdownof the series
switch (Q421and Q423)occurs when the
SID
(shutdown)
input (pin 10) of U233 goes high. The Shutdown Timer,
made up of U829A, R824, C829, R934, CR730, and
CR824,controls this input.
PRIMARY OVER-VOLTAGE SENSING.
The regulated
primary voltage is sensed by the voltage divider R129-
R128, with C528 providing low-pass filtering to remove
high-frequencyswitching spikes. The attenuated signal is
appliedto comparator U840B at the inverting input, while
the noninverting input is connected to the+ 5.1 V refer-
ence from U233. Should the regulated primary voltage
become high enough to raise the inverting input of the
comparator more positive than the noninvertinginput, the
comparator output goes to a low level. As previously
stated, the output of this comparator is wire-ORedto the
output of U840C and drives aninverting clock buffer
U840A. This buffer in turn drives the clockinput of the
monostable flip-flopcircuit used to shut down supply
operation.
PRIMARY OVER-CURRENT SENSING.
The primary
current of T639 through R727 produces a voltage signal
that is filtered by R728 and C728 to remove high-
frequencyswitching spikes. The filtered signalis appliedto
the inverting input of U840C.The noninvertinginput of the
comparator is set at a level defined by the+5.1 V refer-
ence from U233 and voltage divider R935-R836. If an
excessive-currentcondition exists (to the point that the
inverting input of U840C goes more positive than the
noninvertinginput), the comparator output goes low. The
open-collector output of the comparatoris "wire-ORed"
with the open-collector output of the regulated primary
over-voltagecomparator (U840B) and drives U840A,con-
nected as an inverting buffer. Buffer U840A drivesthe
clock input of a CMOS flip-flop in U829, configured as a
monostableflip-flop,usedto shut down supplyoperation.
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