REV DEC 1986
6-36
If any gating signals are absent, backtrack to U470 and/or U370 (on diagram 11) and locate the
defective component.
d. Check for RAMP and RAMP at the bases of Q392 and Q490.
c. Check for SLRMP2 and SLRMP2 at the bases of Q391 and U390.
b. Check for SLRMP1 and SLRMP1 at the bases of Q492 and Q491.
If missing:
a. Test the collector of Q492 and Q391 (diagram 12) for the START pulses.
1. Check that START1 and START2 are present at U841 pin 2 and U842 pin 2 (diagram 13) respec-
tively and that they are coincident.
DIGITAL SECTION TROUBLESHOOTING
Jitter Correction Troubleshooting (schematic diagrams 12 and 13):
On the 2430 under test, select REPET acquisition mode, AUTO LEVEL, VERT Trigger, DC Trigger
COUPLING, and set the SEC/DIV setting to 5 ns. Then select ACQUIRE and connect a probe from the
CH 1 input to TP345 (4C) (found above A10U450, the CH 1 CCD, in the main board).
If there are bands of missing data points every two divisions, only a few data points are placed every
two divisions, or the waveforms are distorted, the problem may be in the Jitter Correction circuitry.
The Jitter Correction circuit has both analog and digital circuits. First check the digital portion to insure
that it is working. If that is ok, then assume that the problem is in the analog portion of the Jitter Circuit.
However, if the Jitter Correction circuit is found to be working correctly and the waveforms are still
distorted (specifically spikes), then the problem may be with the Phase Clock Array Outputs
A10U470. To check U470, see NO SIGNAL ACQUISITIONS in this table.
MISSING DATA
POINTS IN
REPET
c. If these conditions are not true, the problem is probably Phase/Frequency Detector U381 or
amplifier U580.
b. Check that U381 pin 12 is ramping negative with respect to U381 pin 3 (average not absolute)
and TP581 can be as negative as -0.6 V.
Frequency too high at pin 9:
a. Check that U381 pin 3 has negative pulses and that the voltage at U381 pin 12 is positive with
respect to U381 pin 3. The VCO CTL voltage at TP581 can be as high as
+
12 V.
Frequency too low at pin 9:
2. Check U381 pin 9 for 4 MHz if SEC/DIV is 50 us, and 5 MHz if SEC/DIV is 20 os:
NOTE
Use 2430 CURSOR function of 11T/MEto measure the frequency. The cursor position
difference will read out directly in frequency.
1. Check the 4 MHz input to U381 pin 6. If there is no 4 MHz clock at TP174 then go to the Time-
base troubleshooting chart (located in the "Diagrams" section) and troubleshoot the System
Clocks.
Phase-Locked Loop Circuit (schematic diagram 11).
TIMING ERROR
AT 50 f.ls/div
AND FASTER
Table
6-6
(cont)
Maintenance-2430 Service
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