6-82
This test is to check the match of the offsets of the two paths through the peak detectors. A 0 V cal
signal input (DAC value
=
2048) is acquired and the A and B peak detector and D and C peak detec-
tor pairs (see Figure 3-5 in Section 3 of this manual) are matched by iteratively adjusting the appropri-
ate PDOS (peak-detector offset) DACs and remeasuring the difference until offsets are matched. If
matching cannot be accomplished within 1/2 DL for calibration or 1 DL for diagnostics, the test ter-
minates due to acquisition count, and the test result is set to FAIL; otherwise, it passes.
Testing Method:
PEAK DETECTORS A1OU340(CH 2) and A1OU440(CH 1) (schematic diagram 10):
7400
PD-OFFSET
If all other tests are ok, the most probable cause of failure is a defective CCD; replace the failed CCD.
Troubleshooting Procedure:
This test measures the transfer efficiency of the CCD by comparing the gain of columns 2 and 16 of
the CCD B register arrays. To do this, a ±4 division input is applied to the Peak Detector calibration
inputs and acquired. Efficiency loss and apparent offset for the gain are both calculated and stored for
use in dynamic data correction. Efficiency loss of more than 6% will cause an error to be flagged. Test-
ing is performed at two SEC/DIV settings (2
jJ.S
and 500 ns) on all four CCD channels.
Testing Method:
CCD/CLOCK DRIVERS A1OU350and A1OU450(schematic diagram 10):
7300
EFFICIENCY
6. Check the collectors of 0770 and 0870 (0780 and 0880). These should look like waveform 109,
where center screen corresponds to ground. If they do not, make sure the bases are switching on
and off. If they are switching and a collector is not, check the transistor for a collector-to-emitter
short. If not switching on the base, trace the associated DS signal back to the Time Base board.
The timing relationships of the OSAM and the DS signals are shown in waveform 45 through 51 of
the System Clocks schematic (diagram 7).
5. Observe the voltage at pin 7 of U770 and U870 (U780 and U880). It should be similar to waveform
110, except that an offset of up to ± 1.3 V may appear. If this is not the result, check the + 9 V
and the centering voltage (7.5 V ± 1.3 V). If the voltages are correct, check U770 and its associ-
ated transistors and other components for failure.
4. Compare pins 1 and 8 of U560 (pins 9 and 16 for channel 2) to waveform 107. If this waveform
does not appear, check to see that pins 3 and 6 of U560 are switching between 0 and + 15 V. If
they are, then the switch (U560) is bad. If they are not switching, check to see if the base of 0660
(0670) is switching between 0.5 V and 0 V. If it is, the transistor is bad. If it is not, trace OSAM1
(OSAM2) back to the Time Base board.
3. Examine pin 1 of U770A and U870A (U780A and U880A). The input waveform should have an
offset of + 7.5 V, which is center screen in waveform 106. If this waveform does not look right,
check the parts in this section for failures.
2. Verify that pins 1 and 5 (the CCD outputs) of R876 (R886) look similar to waveform 104 (on
schematic diagram 14), with center screen being +5 V. If these waveforms do not appear, trouble-
shoot the CCD/Clock Drivers. Verify that pins 3 and 7 of R876 (R886) resemble waveform 105.
Again, if this waveform does not appear, go to the CCD/Clock Driver troubleshooting.
Table
6-6
(cont)
Maintenance-2430 Service
To Next Page
Loading...
