6-90
b. 0110, U120, and associated circuitry produce a +5 V source that tracks the instrument -5 V
source. The voltage level at U100 pins 17 and 44 should be verified to be +5 V. The decoupled
-5 V power supply voltage at pin 7 of U100 must be present for this circuit and for the circuit
of U100 to function properly.
a. There are only two mode control bits that set up U100. These bits are assumed to be correct if
level 2510 of Extended Diagnostics shows a PASS flag. These two bits set up the 1X or 5X
attenuation for each EXT TRIG channel.
5. EXTERNAL TRIGGER PREAMP A10U100 (schematic diagram 9) is only in the External Trigger
Signal path. It should be verified to
be
functional it FAIL flags appear only at Extended Diagnostics
levels with EXT labels.
EXTERNAL TRIGGER PATH-EXCLUSIVE:
4. The ATG path from Trigger Logic Array U370 to data bus bit DO is also a common path. The AND
logic function of the A Trigger Gate and the B Trigger Gate is performed within Trigger Logic Array
U370. The path from AlB Trigger Gate inputs, through a logic ANDing gate, to the Trigger Logic
Array Output (pin 63, ATG) is asynchronous and direct, delayed only by the propagation delay of
the internal logic gate structures. The ATG signal has a TTL voltage level swing. The ATG output
signal path is through R368 and W110 to buffer U851C (schematic diagram 13) and then through
tristate buffer U761 to the DObit of the System IlP data bus. This path through buffer U761 is not
tested by test 2000 (Register Tests) of Extended Diagnostics, so it must be verified from U370
through U761 to be operational. ATG also clocks Trigger Holdoff flip-flop U872A.
b. WR, ACOSEL, AO-A3, and GADO-GAD7 are the digital control and data lines. These signals are
tested by test number 2510 of the Extended Diagnostics and, if a PASS flag is present, are
assumed to be correct. Otherwise refer to that diagnostics troubleshooting procedure for a
failure of 2510.
a. EPTHO (End Pretrigger Holdoff) from Timebase Controller A 11U670 (schematic diagram 8) via
buffer U680E on the Timebase board. EPTHO must be TTL high for a trigger to occur. If that is
not occurring, see the Timebase and System Clocks troubleshooting chart in the Diagrams
pages at the back of this manual.
3. Trigger Logic Array A10U370 is also common to both the external and internal trigger signal
paths. Related signal inputs that must be correct are:
2. High speed ECL level shift stages, 0250 and 0251 for MAIN GATE and 0150 and 0151 for
DELAY GATE, are common paths for both Internal and External trigger sources. These stages
should have an ECL input swing of less than +3.4 V for logic LO and greater than +4.0 V for
logic HI. The output swing should be greater than -1.6 V for logic LO and less than -1.1 V for
logic HI.
d. Six SR data lines set up the A TRIG SOURCE and B TRIG SOURCE selections. Shift Register
A10U140 (schematic diagram 5) provides these signals, and it is tested by test 2510 of the
Extended Diagnostics. The signals are assumed correct for a PASS flag at that diagnostic
level. If a FAIL flag is present, follow the Troubleshooting Procedure under that diagnostic level.
c. ACD (Acquisition Control Data), A TRIG CLOCK, and B TRIG CLOCK are the signals that load
the internal shift register of U150 with MODE, CPLG, and SLOPE requirements for the trigger
signal. These lines should have TTL level voltage swings, and the A TRIG CLOCK clock and B
TRIG CLOCK signal lines should only have transitions when the associated A or B Trigger
MODE, CPLG, or SLOPE are changed. The ACD data line (U150 pin 46) should be checked for
the presence of voltage transitions.
Table
6-6
(cont)
Maintenance-2430 Service
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