3-7
Low Voltage Power Supply (diagram 22)
The majority of the low voltages required to power the
2430 are produced by a high-efficiency, switching power
supply. Input ac power of either 115 V or 230 V within the
frequency range of 48 Hz to 400 Hz is rectified and used
to qrjve a switching circuit at a frequency of about 50 kHz.
A smaller power transformer is possible with the higher
Video Option (diagram 21)
The Video Option (Option 05) consists of additional
hardware installed in the base 2430 that enhances trigger-
ing on and viewing of composite video signals. Option 05
circuitry contains both Video Processing and Trigger Gen-
eration circuitry. Video Processing stabilizes the input sig-
nal and separates the video sync signals (horizontal and
vertical sync pulses) from the video signal. A wide range of
video signal levels are accommodated by using automatic
gain control of the amplifier that sets the level into the
sync separator. Separated sync pulse are counted to per-
mit the user to select the line number that will produce a
trigger event. Back-porch clamping is available for the
Channel 2 display, and when used, it removes or reduces
the level of power-supply hum that may be accompanying
the composite video signal display.
An audible alarm bell is provided to give the user warn-
ing of events that may require attention. GPIB errors are
typical events that produce the warning bell so that a user
may take notice of the error event. Another instance that
causes the warning bell is an attempted call-up of an
invalid operating condition from either the front panel or
the GPIB. Typically, warning and error messages are also
displayed on the crt to aid the user in determining the
nature of the problem.
Probe power connectors are an option for supplying the
power requirement of active Tektronix probes. The option
consists of two probe power connectors installed on the
rear panel of the scope.
A standard XY Plotter interface provides X-Axis, Y-
Axis, and Pen Lift voltages to drive an analog piotter. The
automatic Pen Lift voltage is polarity selectable for match-
ing the requirements of the external XY Plotter. The output
data normally plotted is the graticule, the SEC/DIV and
VOLTS/DIV scale factors for each plotted waveform, and
the actual waveform data being displayed. Both the grati-
cule and the scale factors may be turned off to prevent
them from being plotted.
Theory of Operation-2430 Service
A second interface is the Word Trigger circuitry used to
control the word recognization patterns of the optional
Word Recognizer probe. All firmware and hardware
(including connectors) required for use of the Word Recog-
nizer probe is supplied as standard equipment. A trigger
produced by the probe (WDTTL) may be internally selected
to trigger the scope, and it may be supplied to an external
device via the WORD TRIG OUT connector on the rear
panel.
System
I/O
(diagram 20)
The System I/O circuits provide the interfaces between
the scope and external devices that may be connected.
Included in the interfaces is a standard general-purpose
interface bus (GPIB) that permits two-way communication
between the System ILP and a GPIB controller or other
IEEE 488-1980 compatible GPIB devices. The GPIB inter-
face permits waveforms, front-panel setups, and other
commands or messages to be both sent and received by
the scope.
High Voltage and CRT (diagram 19)
The High Voltage and CRT circuitry provides the auxili-
ary voltages needed by the CRT to produce a display.
Focus, intensity, trace rotation, astigmatism, geometry, Y-
Axis alignment, heater, and cathode-to-anode accelerating
voltage are all provided by the various circuits included.
These circuits are: the High Voltage Oscillator, the High
Voltage Regulator, the +61 V Supply, the Cathode Sup-
ply, the Anode Multiplier, the DC Restorer, the Focus and
Z-AxiS Amplifiers, the Auto Focus Buffer, and the various
crt adjustment potentiometers.
System Clocks (diagram 7)
The System Clocks circuitry produces the fixed-
frequency clock signals used throughout the scope. A
40 MHz crystat-controlleo oscillator circuit produces the
master clock signal that is divided down to provide the
various system clocks that are needed. Some of the spe-
cial clocks generated are the CCD Data Clocks, used pri-
marily to switch the analog signal samples from the CCDs
to the input of the A/D Converter and switch the converted
data bytes to the Acquisition Latches. The reference fre-
quency (either 4 MHz or 5 MHz) to the Phase Clock Array
in the CCD Clock circuitry (diagram 11) is also selected by
the System Clocks circuitry. A Secondary Clock Generator
state-machine circuit produces three clocking signals to
the Waveform ILPto control the activity of that device.
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