3-9
Analog samples are continually clocked into the CCDs
by the outpsrt clocks of the CCD Phase Clock Array until a
valid trigger is recognized by the Acquisition System. The
Time Base Controller (diagram 8) provides the reference
frequency to the CCD Phase Clock Array via the Refer-
ence Frequency Selector and the Phase-Locked Loop cir-
cuit (diagram 11). Dividers in the CCD Phase Clock Array
synthesize the clocking frequencies needed for saving the
acquisition at the different SEC/DIV settings. The Time
Base Controller also controls the acquisition mode (FISO,
Short-Pipeline, or ROLL) and the storing of acquired sam-
ples into the Acquisition Memory.
At SEC/DIV settings of 50 liS and faster, the signals
are sampled at a faster rate than the maximum conversion
rate of the A/D Converter. This mode is the "fast-in, slow-
out" (FISO) sampling mode. When enough samples have
been stored in the parallel register array of the CCDs to fill
a waveform record after a trigger event, sampling stops
(fast-in). The stored analog samples are then clocked out
of the CCD arrays at a rate that the AID Converter can
handle (hence, slow-out). For SEC/DIV settings slower
than 50 us: the Short-Pipeline sampling mode is used. In
Short-Pipeline, the acquisition rates are slower than the
maximum digitizing rate of the A/D Converter. Samples
are taken at a constant rate in Short-Pipeline mode, but to
account for the slower acquisition rates needed for each
successively slower SEC/DIV setting (from 100 us to 5 s),
samples that are not needed are ignored. Short-Pipeline
mode is so named because the samples do not fill all of
the parallel registers within the CCDs, but take a "short"
serial path through the CCDs (see the "Detailed Circuit
Description" for more information).
The common-mode adjusted signal pairs (two per Peak
Detector) are applied to their corresponding side of the
CCDs. There, they are analog sampled. The process con-
sists of converting the analog voltages into individual,
charged "packets" having a charge directly related to the
voltage amplitude of the signal sample.
Each differential output signal pair from the Peak
Detectors is monitored by a separate Common-Mode
Adjust circuit. These Common-Mode Adjust circuits
(diagram 10) compare the Gammon-mode voltage against
the common-mode adjust voltage output by the System
DAC. The common-mode adjust voltage is set by the Sys-
tem liP to control the overall gain of the CCDs based on
calibration constants stored in the System liP nonvolatile
RAM (diagram 1) as the result of a self calibration.
only one of the output signal pairs from the Peak Detec-
tors. FISO and Short-Pipeline analog sampling modes are
both discussed later in this description and in the "Time
Base Controller and Acquisition Memory" portion of the
Detailed Circuit Description.
Theory of Operation-2430 Service
The signal-sampling process of CCDs (diagram 10)
requires that two differential-signal pairs be available from
each Peak Detector. Each CCD will use one or both out-
put pairs as input signals, depending on the analog sam-
pling mode. Briefly, the FISO sampling mode (fast-in,
slow-out) requires 1056 samples to be shifted into each
CCD. Half of the samples for a channel (528) are shifted
into one side of one CCD, and the other half are shifted
into the second side of the same CCD. The first pair of
differential outputs are shifted into a pair of internal regis-
ters in one half of the CCD on the same phase of the
sample clock. The second pair of differential output signals
are identical to the first pair. This second pair is shifted
into the two internal registers of the second half of the
CCD on the opposite phase of the same sample clock
used to shift in the first pair of output signals. This method
of sampling produces a maximum sampling rate of 200
megasamples per second using a 100 MHz clock fre-
quency. A second sampling method, called the "Short-
Pipeline" mode, uses only half of each CCD and samples
Other inputs to the Peak Detectors control the input
amplifier Bandwidth Limit setting (FULL, 50 MHz, or
20 MHz) and provide for the application of the calibration
signal used for instrument calibration and self diagnostics.
Calibration VOltage levels applied to the Peak Detectors
are generated by the System liP via the System DAC
(diagram 5), DAC MUX 3, and the Cal Ampl circuit
(diagram 6). The System liP selects between either the
normal signal inputs or the calibration signal inputs using
data written to the Acquisition Control Registers. The
bandwidth of the input amplifiers of the Peak Detectors is
also controlled via the Acquisition Control Registers, based
on the user-selected Bandwidth Limit setting.
The System liP controls the operating mode of the
Peak Detectors via control data writes to the Acquisition
Control Registers (diagram 5). Some of the resulting digital
outputs drive control inputs on the Peak Detectors, while
others control the enabling and disabling of the Peak
Detector clock signals from the CCD (charge-coupled
device) Phase Clock Generator (diagram 11). The effect of
this combined action depends on the acquisition mode
selected. For NORMAL and AVG (average) acquisition
modes, the peak-detect function of the Peak Detectors is
disabled and the input signals are only amplified for appli-
cation to the CCDs. For ENVELOPE mode, however, the
peak-detect portion .ot the internal circuitry is enabled, and
the maximum and minimum signal amplitude levels that
occur during a sampling interval are detected. Those max-
imum and minimum values are then amplified and passed
on to the CCDs.
buffered signals are then either amplified further or "peak
detected" and amplified, depending on the acquisition
mode setting.
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