With 0492 on, the charging current is routed through
R497, producing a HI START1 signal and enabling the
RAMP1 Jitter Correction Counter circuit (diagram 13).
The charging current now linearly charges C491 and
the circuit board capacitance positive (holding STOP1 LO
through U490) until the proper edge of the next sample
clock occurs (see Figure 3-7). This switches the SLRMP1
and SLRMP1 signals to their true states, turning off 0491
and turning 0492 on.
RAMP SWITCHING. When Trigger Logic Array U370
(diagram 11) detects that a trigger event has occurred, it
sets the RAMP and RAMP signals to their active (true)
states. The LO RAMP signal turns 0490 off to allow the
integration capacitor to begin a fast charge, and the HI
RAMP signal turns 0392 on to reverse bias CR490 and
remove the clamp circuit from the summing node.
Transistor 0380 and its associated components clamp
the positive peaks of both ramps at +3.2 volts via CR491.
This clamping takes place at SEC/OIV settings slower
than 500 ns/div because the SLRMP signal doesn't occur
soon enough after the RAMP signal starts the ramp to
reverse the ramp slope before the +3.2 V level is reached.
RAMP CLAMPING. The clamping circuit made up of
U590B, CR490, and associated components, holds the
ramp summing-node voltage (collector of 0490) at zero
volts while the circuit is waiting for a trigger to occur (sig-
naled when RAMP and RAMP go to their true states). The
summing-node voltage is applied to U590B on pin 6 where
it is compared to the zero-volt clamp level (ground) on
pin 5. When the summing node attempts to go below
ground while 0490 is on, U590B will conduct more to
maintain the balance at the input pins, thereby clamping
the summing node at zero volts via R592 and CR490.
This charge current is switched through either 0491 or
0492, depending on whether the ramp should be ramping
down slowly or ramping up quickly. When waiting for a
trigger to occur, the SLRMP1 (slow-ramp 1) wi" be LO,
turning 0491 on. Charging current from 0491, which
would normally charge integration capacitor C491 (and the
50 pF circuit-board capacitor), is shunted to -5 volts by
0490, which is turned on by a HI RAMP (fast ramp) signal
applied to its base.
components. The charging current is nominally 20 rnilli-
amperes through R590 and 0493. The voltage drop
across R590 balances the + 7.5 volt reference at pin 2 of
U590A and keeps 0493 turned on just enough to maintain
the balance at the operational amplifier inputs.
3-54
Fast charging rate is determined by the constant
current source formed by U590A, 0493, and associated
The ramp generator consists of a constant current
source used to rapidly charge an integration capacitor
when the trigger event occurs and a second current
source used to discharge the capacitor (more slowly) after
the proper edge of the sample clock occurs. The fast-
charge time is the actual time from the trigger event to the
appropriate sample-clock edge. The time it takes the
slow-discharge mode to discharge C491 gives a numerical
representation (counted) of how high the ramp level
reached when C491 was fast charging; and therefore, the
time of the fast ramp.
Jitter Correction Ramps
Operation of the RAMP1 and RAMP2 circuits is identi-
cal; therefore, only the RAMP1 Jitter Correction circuit will
be described. Both Jitter Correction Ramps are initiated by
the same trigger event, but they are switched to their
slow-discharge mode on opposite edges of the sample
clock. By switching on opposite edges, the trigger point
has two distinct references which define the trigger point,
allowing the System ILP to detect and correct for meta-
stable states of the trigger recognition logic.
The Jitter Correction Ramps located on diagram 12 are
a portion of two dual-ramp timing circuits used to detect
and measure the time difference between a trigger event
and the sample clock. This information is needed when
doing acquisitions at SEC/OIV settings greater that 500 ns
to correctly place the data points obtained on different
trigger events. The Jitter Correction Counters are located
on diagram 13.
JITTER CORRECTION RAMPS
TTL4C is a TTL version of the phase 4 clock for the C
(output) register and runs at a" times except during
RESET. This is one of the signals required by the System
Clock Generators for producing correctly timed Output
Sample Clocks to the CCO Output circuitry (diagram 14)
and the RESET clock to the CCO arrays.
In FISO mode, the TIL1 B (TIL-level phase 1B) signal
runs at
1/16
of the A-register clock rate and is used by the
Time Base Controller to keep track of how many FISO
samples have been taken. Each TIL 1B clock indicates
that 16 sample intervals have occurred. In Short-Pipe
mode, the TTL1B clock runs at the A-register clock rate.
By using the TIL 1B count and the TLO-TL4 data, the
Time Base Controller (U670, diagram 8) can precisely
determine when the acquisition is finished.
Theory of Operation-2430 Service
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