Buffer U761,residingat read location 602Ch,allows the
SystemliP to check the holdoff circuit setup and to moni-
tor the status of the A Trigger (ATG) and trigger holdoff
(ATHO)bits.
The Holdoff Select circuit, under System liP control,
determines which of the Holdoff Current Sources and
which of the integration capacitors will be used to produce
the holdoff ramp. Its outputs are set by the microproces-
sor by writing data into Holdoff Register U762, residingat
address 620Ch. Output bits HOO through H02 (holdoff
control bits 0-2) enable their correspondingcurrent-source
transistor when HI. Bit H03 is used for selection of the
integration capacitor. The FPRESETbit allows the system
processorto reset the Front PanelliP (diagram3).
Holdoff Select
Trigger Holdoff
The Trigger Holdoff circuit consists of a trigger-enabled,
constant current source (actually one of three selectable
sources added to a small permanent source) used to
linearly charge a capacitor (one-of-two selectable cap
values). The resulting integrator output is a linear ramp
whose slope depends on the current-source and
integration-capacitorselection.The ramp is applied to the
Holdoff Comparator where it is compared to the user-
definable(front-panelpot) holdoff-referencelevel.Whenthe
charging ramp crosses that level, the ramp rapidly
discharges(resets)and ends the holdoffcondition.
The Side Board Address Decoder included in the cir-
cuitry is used by the System liP to enablethe appropriate
register or buffer on the Side board to read the Jitter
Correction Counters, select the Holdoff Time, and com-
municatewith the Front PanelliP.
The Calibrator circuit generates a square-wave output
having precise amplitude and frequency characteristics.
The CALIBRATOR signal provided at the front-panel con-
nector is usefulfor adjusting probe compensationand veri-
fying VOLTS/DIV and SEC/DIVcalibration.
The RAMP1 and RAMP2 Jitter Correction Counters
measure the time difference between the asynchronous
trigger event and the actual sampling point of the
waveform data. That information is needed by the System
liP to place the random samples taken in REPET acquisi-
tion mode correctly with respect to data points taken in
the previousacquisitionsto fill the waveform record.
3-56
The Trigger Holdoff circuits allow a delay to occur
between the occurrence of a triggering event and when
the A/B Trigger Generatoris allowedto recognizeanother
trigger event. Variable Holdoff can help the user prevent
double triggering on aperiodic signals (such as complex
digital words).
Circuitry shown in diagram 13 performs a variety of
functions.
TRIGGER HOLDOFF, JITTER COUNTERS,
AND CALIBRATOR
RAMP2.
As mentioned earlier, the RAMP2 Jitter
Correction circuit is running simultaneously,referencedto
the opposite edge of the sample clock. The RAMP2 Jitter
Correction Counter produces a count defining the trigger
point relative to the opposite edge of the sample clock.
Since both ramps have a possibility of an error in their
slow-ramp starting times (due to metastable switching of
the SLRMP1 and SLRMP2 signals)there will always be a
chance of error present in the trigger-position count. The
count from both ramps is checked, and the value closest
to the nominalmidrangecount will be used by the System
liP when placing the repetitively sampled data points. If
both counts are in error, that acquisitionis discarded.
After the Jitter Counter has been read, the RAMP,
RAMP, SLRMP1, and SLRMP1 signals will be reset to
their inactive states. This again clamps the summing-node
voltage at zero volts and reappliesthe charging current to
the nodein preparationfor the next trigger event.
At the time of calibration, the JIT1 GAIN (jitter gain-
ramp 1) value is set to the base of the discharge current
source transistor, 0495, so that the ratio between charg-
ing rate and discharging rate is 1250:1 (approximately
20 mA from the charging current source to approximately
16 liA discharge current from0495). The slow discharge
time of C491 allows the RAMP1 Jitter Correction Counter
to convert the peak amplitude of RAMP1 (dependenton
the time that C491 was allowed to fast charge) into a
count relating trigger-event position to the sample-
clock edge.
Since 0491 is now off, C491 begins the slow-ramp
dischargethrough0495 and R493. When the voltage held
on C491 crosses the switching threshold of U490, STOP1
is switched HI to turn off RAMP1Jitter Correction Counter
at the proper count.
Theory of Operation-2430 Service
To Next Page
Loading...
Need help?
General
