gpmc_clk
gpmc_csn[x]
gpmc_a[10:1]
gpmc_be0n_cle
gpmc_be1n
gpmc_advn_ale
gpmc_oen
gpmc_ad[15:0]
gpmc_wait[x]
Valid Address
D 0
F0
F12
F13
F4
F6
F2
F8
F3
F7
F9
F11
F1
F1
F8
F19
F18
F20
F10
F6
F19
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
www.ti.com
SPRS717H –OCTOBER 2011–REVISED MAY 2015
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
B. In gpmc_wait[x], x is equal to 0 or 1.
Figure 7-17. GPMC and NOR Flash —Synchronous Single Read—(GpmcFCLKDivider = 0)
Copyright © 2011–2015, Texas Instruments Incorporated Peripheral Information and Timings 131
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